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參數(shù)資料
| 型號： | 935269156115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | PLASTIC, SOT-23, SO-5 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 935269156115 |
Philips Semiconductors
Product data
NE56610/11/12-XX
System reset
2001 Jun 19
10
APPLICATION INFORMATION
When the manual reset is not needed, the M/R, manual reset pin is
connected to ground as shown in Figure 18. A capacitor connected
from VCC to ground is recommended when the VCC supply
impedance is appreciably high. This may be the situation with a poor
quality or aged battery.
SL01383
23
1
54
VCC
GND
VOUT
SUB
M/R
RPU
TO VCC
TO CPU
RESET PIN
Figure 18. Typical hard reset circuit
Figure 19 shows a circuit with a manual reset switch. When the
manual switch is closed, VOUT reset is a low voltage state.
Conversely, when it is opened, VOUT reset is a HIGH voltage state.
As a precaution, a clamp diode is placed from the M/R pin to ground
to ensure that the pin does not go below –0.3 V.
SL01384
23
1
54
VCC
GND
VOUT
SUB
M/R
RPU
TO VCC
TO CPU
RESET PIN
RPD
MANUAL
SWITCH
CLAMP
DIODE
Figure 19. Manual Reset circuit
When a manual reset is used, it is suggested a resistor (RPU) be
connected from the M/R pin to ground so as to provide a pull-down
ground reference for the M/R pin when not in use. This will reduce
the possibility of an induced erroneous voltage being imposed on
the M/R pin. This can be a solution in noisy applications where the
manual reset line is of considerable length and subject to picking up
induced voltages. The M/R pin can be pulled to a HIGH voltage
state whenever a manual reset is imposed. The only disadvantage
to this is a small amount of additional current flow through the
pull-down ground reference resistor when the M/R pin is pulled to a
HIGH state.
TEST CIRCUITS
SL01385
23
1
54
VCC
GND
VOUT
SUB
M/R
RPU
A2
A1
10
F/10 V
V1
V2
VCC
VM/R
A = DC AMPMETER
V = DC VOLTMETER
Figure 20. Test circuit 1
SL01386
23
1
54
VCC
GND
VOUT
SUB
M/R
CRT
10
F/10 V
CRT = OSCILLOSCOPE
INPUT
PULSE
RPU
CL
100 pF
5.0 V
VS(typ) + 0.4 V
VS(typ) – 0.4 V
0 V
INPUT PULSE
Figure 21. Test circuit 2
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