參數(shù)資料
型號(hào)： 935269149115
廠商： NXP SEMICONDUCTORS
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝： PLASTIC, SOT-23, SO-5
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 157K
代理商： 935269149115
Philips Semiconductors
Product data
NE56610/11/12-XX
System reset
2001 Jun 19
4
ELECTRICAL CHARACTERISTICS
Characteristics noted with M/R pin connected to ground. Typical values reflect appropriate average value at Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TEST
CIRCUIT
PART #
MIN.
TYP.
MAX.
UNIT
VS
Threshold detection
VCC falling; RL = 470 ; VOL ≤ 0.4 V
–45
4.3
4.5
4.7
V
–42
4.0
4.2
4.4
V
–39
3.7
3.9
4.1
V
–29
2.75
2.90
3.05
V
–27
2.55
2.70
2.85
V
–25
2.35
2.50
2.65
V
VS
Hysteresis
VS = VSH (rising VCC) – VSL (falling VCC);
RL = 470
1
Fig. 20
All
30
50
100
mV
TC/VS
Threshold temperature
coefficient
RL = 470 ;
–20
°C ≤ Tamb ≤ +75 °C
All
–
±0.01
–
%/
°C
VOL
LOW-level output voltage
VCC = VS(min) – 0.05 V; RL = 470
All
–
0.01
0.4
V
ILO
Output leakage current
VCC = 10 V
All
–
±0.1
A
ICCL
Circuit current (output LOW)
VCC = VS(min) – 0.05 V; RL = ∞
All
–
300
500
A
ICCH
Circuit current (output HIGH)
VCC = VS(typ) / 0.85 V; RL = ∞
All
–
15
25
A
tDLH
Reset delay time HIGH
(Note 1)
RL = 4.7 k; CL = 100 pF
NE56610
30
50
75
ms
(Note 1)
2
NE56611
60
100
150
ms
2
Fig. 21
NE56612
120
200
300
ms
tDHL
Reset delay time LOW
(Note 2)
RL = 4.7 k; CL = 100 pF
All
–
20
–
s
VOPL
Operating supply voltage
RL = 4.7 k; VOL ≤ 0.4 V
All
–
0.65
0.85
V
IOL1
Output sink current 1
VCC = VS(min) – 0.05 V; RL = 0
1
Fig 20
All
–8.0
–
mA
IOL2
Output sink current 2
VCC = VS(min) – 0.05 V; RL = 0;
–20
°C ≤ Tamb ≤ +75 °C
Fig. 20
All
–6.0
–
mA
VM/RH
HIGH-level M/R threshold
voltage (Note 3)
All
2.0
–
V
IM/RH
HIGH-level M/R threshold
current
VM/RH = 2.0 V
All
–
10
60
A
VM/RL
LOW-level M/R threshold
voltage
All
–0.3
–
0.8
V
tM/R
M/R pulse width (Note 4)
All
15
–
s
NOTES:
1. tDLH measured with VCC = (VS(typ) – 0.4 V) and abruptly transitioning to (VS(typ) + 0.4 V). tDLH is the duration from VCC transition HIGH to
output transition HIGH.
2. tDHL measured with VCC = (VS(typ) + 0.4 V) and abruptly transitioning to (VS(typ) – 0.4 V). tDHL is the duration from VCC transition LOW to
output transition LOW.
3. Ramp M/R voltage until output RESET goes LOW.
4. Minimum M/R pulse width for detection.
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