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參數(shù)資料
| 型號： | 935268885112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 935268885112 |
Philips Semiconductors
Product specification
PCK2509SA
50–150 MHz 1:9 SDRAM clock driver
2
2000 Dec 01
853–2228 25137
FEATURES
Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
JEDEC compliant operation—PLL reamins locked when outputs
are disabled.
See PCK2509SL for low power version where PLL goes into
standby when outputs are disabled..
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(t
phase error – jitter) at 100 to133 MHz = ±50 ps
Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew < 200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of five outputs and
one bank of four outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
Inputs compatible with 2.5 V and 3.3 V ranges
See page 7 for Characteristic curves
DESCRIPTION
The PCK2509SA is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2509SA operates at 3.3 V VCC and
is input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine
low-skew, low-jitter copies of CLK. Output signal duty cycles are
adjusted to 50 percent, independent of the duty cycle at CLK. Each
bank of outputs can be enabled or disabled separately via the
control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low,
the outputs are disabled to the logic–low state.
Unlike many products containing PLLs, the PCK2509SA does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2509SA requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up
and application of a fixed-frequency, fixed-phase signal at CLK, and
following any changes to the PLL reference or feedback signals. The
PLL can be bypassed for test purposes by strapping AVCC to ground.
The PCK2509SA is characterized for operation from 0
°C to +70°C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
CLK
AVCC
VCC
2Y0
1Y0
2Y1
GND
1Y1
GND
2Y3
1Y2
2Y2
GND
VCC
FBIN
GND
1Y3
1Y4
VCC
1G
FBOUT
SW00389
2G
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic TSSOP
0
°C to +70 °C
PCK2509SADH
SOT355-1
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