- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24811 > 935268565118 (NXP SEMICONDUCTORS) 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | 935268565118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-163-1, SO-20 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 137K |
| 代理商： | 935268565118 |
Philips Semiconductors
Product data
PCA9544
4-channel I2C multiplexer with interrupt logic
2002 Jul 26
12
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I2C-BUS
FAST-MODE I2C-BUS
UNIT
MIN
MAX
MIN
MAX
tpd
Propagation delay from SDA to SDn or SCL to SCn
—
0.31
—
0.31
ns
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
Bus free time between a STOP and START condition
4.7
—
1.3
—
s
tHD;STA
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
—
0.6
—
s
tLOW
LOW period of the SCL clock
4.7
—
1.3
—
s
tHIGH
HIGH period of the SCL clock
4.0
—
0.6
—
s
tSU;STA
Set-up time for a repeated START condition
4.7
—
0.6
—
s
tSU;STO
Set-up time for STOP condition
4.0
—
0.6
—
s
tHD;DAT
Data hold time
02
3.45
02
0.9
s
tSU;DAT
Data set-up time
250
—
100
—
ns
tR
Rise time of both SDA and SCL signals
—
1000
20 + 0.1Cb3
300
ns
tF
Fall time of both SDA and SCL signals
—
300
20 + 0.1Cb3
300
s
Cb
Capacitive load for each bus line
—
400
—
400
s
tSP
Pulse width of spikes which must be suppressed
by the input filter
—
50
—
50
ns
tVD:DATL
Data valid (HL)
—
1
—
1
s
tVD:DATH
Data valid (LH)
—
0.6
—
0.6
s
tVD:ACK
Data valid Acknowledge
—
1
—
1
s
INT
tiv
INTn to INT active valid time
—
4
—
4
s
tir
INTn to INT inactive delay time
—
2
—
2
s
Lpwr
LOW level pulse width rejection or INTn inputs
10
—
1
—
ns
Hpwr
HIGH level pulse width rejection or INTn inputs
500
—
500
—
ns
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
tSP
tBUF
tHD;STA
P
S
tLOW
tR
tHD;DAT
tF
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
SU00645
Figure 14. Definition of timing on the I2C-bus
相關PDF資料 |
PDF描述 |
|---|---|
| 935272002118 | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PQCC20 |
| 935268565112 | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO20 |
| 08-0351-00-01 | SCHUTZKAPPE EINBAUSTECKER |
| 08-0352-00-01 | SCHUTZKAPPE EINBAUDOSE |
| 09-0404-890-02 | EINBAUDOSE LEITERPLATTENSTIFT 2POL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
發(fā)布緊急采購，3分鐘左右您將得到回復。