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參數(shù)資料
| 型號(hào)： | 935268471118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 116K |
| 代理商： | 935268471118 |
Philips Semiconductors
Product data
PCA9542
2-channel I2C multiplexer and interrupt logic
2002 Mar 28
4
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9542 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
A1 A0
0A2
SW00862
1
R/W
FIXED
HARDWARE SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9542 which will be stored
in the Control Register. If multiple bytes are received by the
PCA9542, it will save the last byte received. This register can be
written or read via the I2C bus.
X
INT1 INT0
B2
B1
B0
CHANNEL SELECTION BITS
INTERRUPT BITS
X
SW00477
X
(READ ONLY)
(READ/WRITE)
6
5
4
2
1
0
7
3
ENABLE BIT
Figure 4. Control register
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9542 has
been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a stop condition has been placed
on the I2C bus. This ensures that all SCx/SDx lines will be in a HIGH
state when the channel is made active, so that no false conditions
are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
D7
D6
INT1
INT0
D3
B2
B1
B0
COMMAND
X
0
X
No channel
selected
X
1
0
Channel 0
enabled
X
1
0
1
Channel 1
enabled
X
1
X
No channel
selected
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds
the PCA9542 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9542 registers and
I2C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
INTERRUPT HANDLING
The PCA9542 provides 2 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9542 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte.
Bits 4 – 5 of the control byte correspond to channels 0 – 1 of the
PCA9542, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9542 and read the contents of the control
byte to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9542 to select this
channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to VDD through a
pull-up resistor.
Table 2. Control Register; Read — Interrupt
D7
D6
INT1
INT0
D3
B2
B1
B0
COMMAND
0
X
0
X
No interrupt
on channel 0
0
X
1
X
Interrupt on
channel 0
0
X
No interrupt
on channel 1
0
1
X
Interrupt on
channel 1
NOTE: The 2 interrupts can be active at the same time.
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