
Philips Semiconductors
Product specification
74ALVC16334A
16-bit registered driver with inverted register enable
(3-State)
2000 Mar 14
8
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V AND
VCC = 2.7 V RANGE
VM = 1.5 V
VX = VOL + 0.3 V
VY = VOH – 0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = 2.7 V
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
An
INPUT
tPHL
tPLH
VOL
VI
GND
VOH
Yn
OUTPUT
SH00132
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
VI
GND
VOH
VOL
tPHL
tPLH
tW
VM
SH00165
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
An
INPUT
LE
INPUT
tSU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
tSU
th
VI
GND
VI
GND
VM
SH00166
VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 3. Data set-up and hold times for the An input to the
LE input
CP INPUT
Yn OUTPUT
VI
GND
VOH
VOL
tPHL
tPLH
tW
1/fMAX
SH00135
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 4. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
VI
GND
An INPUT
VI
GND
VOH
Yn OUTPUT
VOL
CP INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SH00136
VM
VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
tPLZ
tPZL
VI
nOE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
tPHZ
VM
tPZH
VX
VY
SH00137
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times