參數(shù)資料
型號： 935267360512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOP-20
文件頁數(shù)： 5/69頁
文件大?。?/td> 352K
代理商： 935267360512
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
11
Table 2. Example A/D Conversion Times
CPU Clock Rate
RCCLK = 0
RCCLK = 1
CPU Clock Rate
RCCLK = 0
minimum
nominal
maximum
32 kHz
NA
563.4
s
659
s
757
s
1 MHz
186
s
32.4
s
39.3
s
48.9
s
4 MHz
46.5
s
18.9
s
23.6
s
30.1
s
11.0592 MHz
16.8
s
16
s
20.2
s
27.1
s
12 MHz
15.5
s
16 MHz
11.6
s
20 MHz
9.3
s
Note: Do not clock ADC from the RC oscillator when MCU clock is greater than 4 MHz.
AD0 (P0.3)
AD1 (P0.4)
VREF+ = VDD
AADR1
AD2 (P0.5)
AD3 (P0.6)
00
01
10
11
VREF- = VSS
ADCON
A/D Converter
AADR0
DAC0
(A/D result)
SU01356
Figure 3. A/D Converter Connections
The A/D in Power Down and Idle Modes
While using the CPU clock as the A/D clock source, the Idle mode
may be used to conserve power and/or to minimize system noise
during the conversion. CPU operation will resume and Idle mode
terminate automatically when a conversion is complete if the A/D
interrupt is active. In Idle mode, noise from the CPU itself is
eliminated, but noise from the oscillator and any other on-chip
peripherals that are running will remain.
The CPU may be put into Power Down mode when the A/D is
clocked by the on-chip RC oscillator (RCCLK=1). This mode gives
the best possible A/D accuracy by eliminating most on-chip noise
sources.
If the Power Down mode is entered while the A/D is running from the
CPU clock (RCCLK=0), the A/D will abort operation and will not
wake up the CPU. The contents of DAC0 will be invalid when
operation does resume.
When an A/D conversion is started, Power Down or Idle mode must
be activated within two machine cycles in order to have the most
accurate A/D result. These two machine cycles are counted at the
CPU clock rate. When using the A/D with either Power Down or Idle
mode, care must be taken to insure that the CPU is not restarted by
another interrupt until the A/D conversion is complete. The possible
causes of wakeup are different in Power Down and Idle modes.
A/D accuracy is also affected by noise generated elsewhere in the
application, power supply noise, and power supply regulation. Since
the 87LPC768 power pins are also used as the A/D reference and
supply, the power supply has a very direct affect on the accuracy of
A/D readings. Using the A/D without Power Down mode while the
clock is divided through the use of CLKR or DIVM has an adverse
effect on A/D accuracy.
相關(guān)PDF資料
PDF描述
935267487512 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
08-70-1028 Crimp Socket Contact; Wire Size (AWG):28-22; Contact Material:Brass; Contact Plating:Tin
08-70-1029 Connector Contact,SKT,CRIMP Terminal
08-70-1031 Connector Contact,SKT,CRIMP Terminal
08-70-1039 Crimp Socket Contact; Wire Size (AWG):28-22; Contact Material:Phosphor Bronze; Contact Plating:Tin; Contact Termination:Crimp; For Use With:Molex 5264-N Series Shrouded Crimp Terminal Housings; Pack Quantity:1; Series:5263
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