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參數(shù)資料
| 型號(hào)： | 935266896557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-64 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 250K |
| 代理商： | 935266896557 |
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1999 Feb 24
3
Philips Semiconductors
Product specication
Triple high-speed Analog-to-Digital
Converter (ADC)
TDA8752A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
for R, G and B channels
4.75
5.0
5.25
V
VDDD
logic supply voltage
for I2C-bus and 3-wire
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output stages supply voltage
for R, G and B channels
4.75
5.0
5.25
V
VCCA(PLL)
analog PLL supply voltage
4.75
5.0
5.25
V
VCCO(PLL)
output PLL supply voltage
4.75
5.0
5.25
V
ICCA
analog supply current
120
mA
IDDD
logic supply current
for I2C-bus and 3-wire
1.0
mA
ICCD
digital supply current
40
mA
ICCO
output stages supply current
fCLK = 100 MHz;
ramp input
6
mA
ICCA(PLL)
analog PLL supply current
28
mA
ICCO(PLL)
output PLL supply current
5
mA
fCLK
maximum clock frequency
TDA8752A/6
60
MHz
TDA8752A/8
100
MHz
fref(PLL)
PLL reference clock frequency
15
280
kHz
fVCO
VCO output clock frequency
12
100
MHz
INL
DC integral non linearity
from analog input to
digital output; full-scale;
ramp input;
fCLK = 100 MHz
±0.5
±1.5
LSB
DNL
DC differential non linearity
from analog input to
digital output; full-scale;
ramp input;
fCLK = 100 MHz
±0.5
±1.0
LSB
G
amp/T
amplier gain stability as a function of
temperature
Vref = 2.5 V with
100 ppm/
°C maximum
200
ppm/
°C
B
amplier bandwidth
3 dB; T
amb =25 °C
250
MHz
tset
settling time of the ADC block plus AGC
input signal settling
time < 1 ns; Tamb =25 °C
6ns
DRPLL
PLL divider ratio
100
4095
Ptot
total power consumption
fCLK = 100 MHz;
ramp input
1.0
W
jPLL(rms)
maximum PLL phase jitter (RMS value)
fref = 66.67 kHz;
fCLK = 100 MHz
0.3
ns
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