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參數(shù)資料
| 型號(hào)： | 935266674118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | 935266674118 |
Philips Semiconductors
Product data
PCA9540
2-channel I2C multiplexer
2002 May 13
10
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I2C-BUS
FAST-MODE
I2C-BUS
UNIT
MIN
MAX
MIN
MAX
tpd
Propagation delay from SDA to SDn or SCL to SCn
—
0.31
—
0.31
ns
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
Bus free time between a STOP and START condition
4.7
—
1.3
—
s
tHD;STA
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
—
0.6
—
s
tLOW
LOW period of the SCL clock
4.7
—
1.3
—
s
tHIGH
HIGH period of the SCL clock
4.0
—
0.6
—
s
tSU;STA
Set-up time for a repeated START condition
4.7
—
0.6
—
s
tSU;STO
Set-up time for STOP condition
4.0
—
0.6
—
s
tHD;DAT
Data hold time
02
3.45
02
0.9
s
tSU;DAT
Data set-up time
250
—
100
—
ns
tR
Rise time of both SDA and SCL signals
—
1000
20 + 0.1Cb3
300
ns
tF
Fall time of both SDA and SCL signals
—
300
20 + 0.1Cb3
300
s
Cb
Capacitive load for each bus line
—
400
—
400
s
tSP
Pulse width of spikes which must be suppressed
by the input filter
—
50
—
50
ns
tVD:DATL
Data valid (HL)
—
1
—
1
s
Data valid (LH)
—
0.6
—
0.6
s
tVD:ACK
Data valid Acknowledge
—
1
—
1
s
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
tSP
tBUF
tHD;STA
P
S
tLOW
tR
tHD;DAT
tF
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
SU00645
Figure 13. Definition of timing on the I2C-bus
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