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參數(shù)資料
| 型號： | 935264449557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.5 X 5.5 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, FBGA-96 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 77K |
| 代理商： | 935264449557 |
1999 Nov 24
8
Philips Semiconductors
Product specication
32-bit edge-triggered D-type ip-op with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
AC CHARACTERISTICS
GND = 0 V; tr =tf ≤ 2.5 ns; CL = 50 pF; RL = 500 .
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25 °C.
AC WAVEFORMS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 40 to +85 °C
UNIT
WAVEFORMS
VCC (V)
MIN.
TYP.(1)
MAX.
tPHL/tPLH
propagation delay
nCP to nQn
see Figs 4 and 7
2.7
1.5
6.4
ns
3.0 to 3.6
1.5
3.8
5.4
ns
tPZH/tPZL
3-state output enable time
nOE to nQn
see Figs 6 and 7
2.7
1.5
6.6
ns
3.0 to 3.6
1.5
3.6
5.6
ns
tPHZ/tPLZ
3-state output disable time
nOE to nQn
see Figs 6 and 7
2.7
1.5
6.5
ns
3.0 to 3.6
1.5
3.9
5.5
ns
tW
nCP pulse width HIGH
see Figs 4 and 7
2.7
3.0
ns
3.0 to 3.6
3.0
1.5
ns
tsu
set-up time nDn to nCP
see Figs 5 and 7
2.7
2.0
ns
3.0 to 3.6
1.9
0.3
ns
th
hold time nDn to nCP
see Figs 5 and 7
2.7
1.5
ns
3.0 to 3.6
+1.1
0.3
ns
fmax
maximum clock frequency
see Figs 4 and 7
2.7
80
MHz
3.0 to 3.6
100
MHz
handbook, full pagewidth
MNA499
nCP input
nQn output
tPHL
tPLH
tW
VM
VOH
VI
GND
VOL
VM
1/fmax
VM
Fig.4 Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
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