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參數(shù)資料
| 型號： | 935264449518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 32 1-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.5 X 5.5 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, FBGA-96 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 77K |
| 代理商： | 935264449518 |
1999 Nov 24
9
Philips Semiconductors
Product specication
32-bit edge-triggered D-type ip-op with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
handbook, full pagewidth
MNA500
GND
th
tsu
th
tsu
VM
VI
VOH
VOL
VI
nQn output
nCP input
nDn input
Fig.5 Set-up and hold times for inputs (nDn) to inputs (nCP).
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state output enable and disable times.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VX =VOL + 0.3 V at VCC ≥ 2.7 V;
VX =VOL + 0.1 V at VCC < 2.7 V.
VY =VOH 0.3VatVCC ≥ 2.7 V;
VY =VOH 0.1VatVCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
handbook, full pagewidth
MNA478
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
tPZL
tPZH
VM
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