參數(shù)資料
型號： 935263937118
廠商： NXP SEMICONDUCTORS
元件分類： 調(diào)諧器
英文描述： 2-BAND, VIDEO TUNER, PDSO28
封裝： PLASTIC, SOT-341, SSOP-28
文件頁數(shù)： 5/48頁
文件大?。?/td> 242K
代理商： 935263937118
2000 Aug 02
13
Philips Semiconductors
Product specication
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
8.3
3-wire bus data format: pin SW to VCC or
open-circuit
During a HIGH level on pin CE/AS (enable line), the data
is clocked into the data register at the HIGH-to-LOW
transition of the clock (see Figs 4, 5 and 6).
The first four bits control the PMOS ports and are loaded
into the internal band-switch register on the 5th rising edge
of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the enable line when an
18-bit or 19-bit data word is transmitted. When a 27-bit
data word is transmitted, the frequency bits are loaded into
the frequency register on the 20th rising edge of the clock
pulse and the control bits at the HIGH-to-LOW transition of
the enable line (see Fig.6).
In this 27-bit data format mode the reference divider is
given by bits RSA and RSB (see Table 8).
The test bits T2, T1 and T0, the charge pump bit CP, the
ratio select bit RSB and bit OS can only be selected or
changed with a 27-bit transmission. They remain
programmed if an 18-bit or 19-bit transmission occurs.
Only bit RSA is controlled by the transmission length when
the 18-bit or 19-bit format is used. When an 18-bit data
word is transmitted, the most significant bit of the divider
(bit N14) is internally set to logic 0 and bit RSA is set to
logic 1. When a 19-bit data word is transmitted, bit RSA is
set to logic 0.
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits. A data word of
less than 18 bits will not affect the frequency register of the
device.
The definition of the bits is unchanged compared to the
I2C-bus mode.
8.3.1
POWER-ON RESET
The power-on detection threshold voltage VPOR is set to
3.2 V at room temperature. Below this threshold the device
is reset to the power-on state.
At power-on state the following actions take place:
The charge pump current is set to 280 A
The test bits T2, T1 and T0 are set to logic ‘001’
The divider bit RSB is set to logic 1
The tuning voltage output is disabled
The tuning amplifier control bit OS is automatically reset
to logic 0 in 18-bit and 19-bit modes when the first data
word is received to allow normal operation
Port register UHF is ‘off’, which means that the UHF
oscillator and the UHF mixer are switched off.
Consequently, the VHF oscillator and the VHF mixer are
switched on. Port registers VHFL and VHFH are ‘off’,
which means that the VHF tank circuit is operating in the
VHF low sub-band. The tuning amplifier is switched off
until the first transmission. In that case, the tank circuit
is supplied with the maximum tuning voltage.
The oscillator is therefore operating at the end of the
VHF low sub-band
The reference divider ratio is set to 64 or 128 if the first
sequence to the device has 18 bits or 19 bits
respectively; if the sequence has 27 bits, the reference
divider ratio is set by bits RSA and RSB (see Table 8).
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