參數(shù)資料
型號(hào)： 935263936118
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 調(diào)諧器
英文描述： 2-BAND, VIDEO TUNER, PDSO28
封裝： PLASTIC, SOT-341, SSOP-28
文件頁(yè)數(shù)： 34/48頁(yè)
文件大?。?/td> 242K
代理商： 935263936118
2000 Aug 02
4
Philips Semiconductors
Product specication
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
Depending on the voltage applied to pin SW (see Table 2)
the device is operating in the I2C-bus mode or 3-wire bus
mode.
In the 3-wire bus mode, pin LOCK/ADC is the ‘lock’ output
of the PLL and is at LOW level when the PLL is locked.
Lock detector bit FL of the status byte is set to logic 1 when
the loop is locked and is read on the SDA line during a
READ operation in I2C-bus mode only.
In the I2C-bus mode only, pin LOCK/ADC is the ADC input
for digital AFC control. The ADC code is read during a
READ operation on the I2C-bus.
In the test mode, in both I2C-bus mode and 3-wire bus
mode, pin LOCK/ADC is used as a test output for fREF and
1
2fDIV.
3.1
I2C-bus format
Five serial bytes (including the address byte) are required
to address the device, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I2C-bus addresses which can be selected by applying a
specific voltage to pin CE/AS.
3.2
3-wire bus format
Data is transmitted to the device during a HIGH level on
pin CE/AS (enable line). The device is accessible with
18-bit and 19-bit data formats (see Figs 4 and 5). The first
four bits are used to program the PMOS ports and the
remaining bits control the programmable divider. A 27-bit
data format (see Fig.6) may also be used to set the charge
pump current, the reference divider ratio and the test
modes.
It is not allowed to address the device with words whose
length is different from 18, 19 or 27 bits.
Table 1
Data word length for 3-wire bus format
Note
1. The selection of the reference divider is given by an
automatic identification of the data word length. When
the 27-bit format is used, the reference divider is
controlled by bits RSA and RSB (see Table 8). More
details are given in Section 8.3.
DATA WORD
REFERENCE
DIVIDER(1)
FREQUENCY
STEP
18-bit
64
62.50 kHz
19-bit
128
31.25 kHz
27-bit
programmable
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