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參數(shù)資料
| 型號： | 935263510112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO8 |
| 封裝： | PLASTIC, SOT-96, SO-8 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大小： | 236K |
| 代理商： | 935263510112 |
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2000 Mar 28
10
Philips Semiconductors
Product specication
Gigabit Ethernet/Fibre Channel
transimpedance amplier
TZA3043; TZA3043B
Notes
1. PSRR is defined as the ratio of the equivalent current change at the input (
IIPhoto) to a change in supply voltage:
For example, a +10 mV disturbance on VCC at 10 MHz will typically add an extra 20 nA to the photodiode current.
The external capacitor between pins DREF and GND has a large impact on the PSRR. The specification is valid with
an external capacitor of 1 nF.
2. The pulse width distortion (PWD) is <5% over the whole input current range. The PWD is defined as:
where T is the clock period. The PWD is measured differentially with
PRBS pattern of 1023.
3. All In(tot) measurements were made with an input capacitance of Ci = 1 pF. This was comprised of 0.5 pF for the
photodiode itself, with 0.3 pF allowed for the printed-circuit board layout and 0.2 pF intrinsic to the package. Noise
performance is measured differentially.
Data outputs: pins OUT and OUTQ
Vo(cm)
common mode output voltage
AC coupled; RL =50
VCC 2VCC 1.7 VCC 1.4 V
Vo(se)(p-p)
single-ended output voltage
(peak-to-peak value)
AC coupled; RL =50 ;
input current 100
A (p-p)
75
200
330
mV
VOO
differential output offset
voltage
100
+100
mV
Ro
output resistance
single-ended; DC tested
40
50
62
tr, tf
rise time, fall time
VCC = 5 V; 20% to 80%;
input current <20
A (p-p)
285
430
ps
VCC = 3.3 V; 20% to 80%;
input current <20
A (p-p)
300
460
ps
Automatic gain control loop: pad AGC
Ith(AGC)
AGC threshold current
referenced to the peak
input current; tested at
10 MHz
25
A
tatt(AGC)
AGC attack time
5
s
tdecay(AGC)
AGC decay time
10
ms
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PSRR
I
IPhoto
V
CC
--------------------
=
PWD
pulse width
T
------------------------------
1
–
100%
×
=
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