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參數(shù)資料
| 型號： | 935263359112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 312K |
| 代理商： | 935263359112 |
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Philips Semiconductors
Preliminary specification
87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP
2000 Jun 01
41
SU01182
WATCHDOG
INTERRUPT
S
Q
20-BIT COUNTER
STATE CLOCK
WDTE (UCFG1.7)
BOD (xxx.x)
POR (xxx.x)
WATCHDOG
RESET
CLEAR
8 MSBs
8 TO 1 MUX
WATCHDOG
FEED DETECT
WDOVF
(WDCON.5)
WDS2–0
(WDCON.2–0)
WDTE + WDRUN
WDCLK * WDTE
500 kHz
R/C OSCILLATOR
ENABLE
CLOCK OUT
R
Figure 33. Block Diagram of the Watchdog Timer
BIT
SYMBOL
FUNCTION
WDCON.7, 6
—
Reserved for future use. Should not be set to 1 by user programs.
WDCON.5
WDOVF
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
WDCON.4
WDRUN
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
WDCON.3
WDCLK
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
WDCON.2–0 WDS2–0
Watchdog rate select.
WDS2–0
Timeout Clocks
Minimum Time
Nominal Time
Maximum Time
0 0 0
8,192
10 ms
16 ms
23 ms
0 0 1
16,384
20 ms
32 ms
45 ms
0 1 0
32,768
41 ms
65 ms
90 ms
0 1 1
65,536
82 ms
131 ms
180 ms
1 0 0
131,072
165 ms
262 ms
360 ms
1 0 1
262,144
330 ms
524 ms
719 ms
1 1 0
524,288
660 ms
1.05 sec
1.44 sec
1 1 1
1,048,576
1.3 sec
2.1 sec
2.9 sec
WDS0
SU01183
WDS1
WDS2
WDCLK
WDRUN
WDOVF
—
0
1
2
3
4
5
6
7
WDCON
Reset Value:
S 30h for a watchdog reset.
S 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
S 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
Not Bit Addressable
Address: A7h
Figure 34. Watchdog Timer Control Register (WDCON)
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