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參數(shù)資料
| 型號： | 935263158551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 19/67頁 |
| 文件大?。?/td> | 516K |
| 代理商： | 935263158551 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
26
The contents of the Compare Registers CM0, CM1 and CM2 are
continuously compared with the counter value of Timer T2. When a
match occurs, an interrupt may be invoked. A match of CM0 sets
the bits 0–5 of Port 4, a CM1 match resets these bits and a CM2
match toggles bits 6 and 7 of Port 4, provided these functions are
enabled by the STE respectively RTE registers. A match of CM0
and CM1 at the same time results in resetting bits 0–5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
Figure 24. Interrupt flag register (TM2IR).
7
6
54
321
0
TM2IR (C8H)
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Table 19.
Description of TM2IR bits
SYMBOL
BIT
FUNCTION
T2OV
TM2IR.7
Timer T2 16-bit overflow interrupt flag
CMI2
TM2IR.6
CM2 interrupt flag
CMI1
TM2IR.5
CM1 interrupt flag
CMI0
TM2IR.4
CM0 interrupt flag
CTI3
TM2IR.3
CT3 interrupt flag
CTI2
TM2IR.2
CT2 interrupt flag
CTI1
TM2IR.1
CT1 interrupt flag
CTI0
TM2IR.0
CT0 interrupt flag
Figure 25. Set enable register (STE).
7
6
54
321
0
STE (EEH)
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Table 20.
Description of STE bits
SYMBOL
BIT
FUNCTION
TG47
STE.7
If “1” then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle
TG46
STE.6
If “1” then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle
SP45
STE.5
If “1” then P4.5 is set on a match between CM0 and Timer T2
SP44
STE.4
If “1” then P4.4 is set on a match between CM0 and Timer T2
SP43
STE.3
If “1” then P4.3 is set on a match between CM0 and Timer T2
SP42
STE.2
If “1” then P4.2 is set on a match between CM0 and Timer T2
SP41
STE.1
If “1” then P4.1 is set on a match between CM0 and Timer T2
SP40
STE.0
If “1” then P4.0 is set on a match between CM0 and Timer T2
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