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參數(shù)資料
| 型號： | 935263158518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 10/67頁 |
| 文件大小： | 516K |
| 代理商： | 935263158518 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
18
6.6
Analog/Digital Converter (ADC)
The P8xC557E6 A/D Converter is a 10–bit, successive
approximation ADC with 8 multiplexed analog input channels. It
additionally contains a high input impedance comparator, a DAC
built with 1024 series resistors and analog switches, registers and
control logic.
Input voltage range is from AVref– (typical 0V) to AVref+ (typical +5V).
A set of 8 buffer registers (10–bit) store the conversion results of the
proper analog input channel each.
11 Special Function Registers (SFR) perform the user software
interface to the ADC: a control SFR (ADCON), an analog port
scan–select SFR (ADPSS), 8 input channel related conversion
result SFR with the 8 lower result bits (ADRSL0...ADRSL7), one
common result SFR for the upper 2 result bits (ADRSH). An extra
SFR (P5) allows for reading digital input port data as an alternative
function of the 8 analog input pins.
In order to have a minimum of ADC service overhead in the
microcontroller program, the ADC is able to operate autonomously
within its user configurable autoscan function.
The functional diagram of the ADC is shown in Figure 14.
Feature Overview:
10–bit resolution.
8 multiplexed analog inputs.
Programmable autoscan of the analog inputs.
Bit oriented 8–bit scan–select register to select analog inputs.
Continuous scan or one time scan configurable from 1 to 8 analog
inputs.
Start of a conversion by software or with an external signal.
Eight 10–bit buffer registers, one register for each analog input
channel.
Interrupt request after one channel scan loop.
Programmable prescaler (dividing by 2, 4, 6, 8) to adapt to
different system clock frequencies.
Conversion time for one A/D conversion: 15 s ... 50 s
Differential non–linearity
:
DLe
±1 LSB.
Integral non–linearity
:
ILe
±2 LSB.
Offset error
:
OSe
±2LSB.
Gain error
:
Ge
±0.4 %.
Absolute voltage error
:
Ae
±3 LSB.
Channel to channel matching
:
Mctc
±1LSB.
Crosstalk between analog inputs : Ct < –60dB. @100 kHz.
Monotonic and no missing codes.
Separated analog (AV
DD, AVSS) and digital (VDD, VSS) supply
voltages.
Reference voltage at two special pins : AV
REF– and AVREF+.
For further information on the ADC characteristics, refer to the “DC
CHARACTERISTICS” section.
Figure 14. Functional diagram of AD converter.
+
–
88
8
2
10
COMPARATOR
SAR
DAC
8x
10–bit result
registers
SCAN LOGIC
ADPSS
ADCON
2 LATCHES
Read
ADRS
H
Read
ADRSLn
ANALOG
Mux.
ADC0
ADC7
AVref+
AVref–
AVDD1
AVSS1
ADEXS
INTERNAL BUS
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