參數(shù)資料
型號(hào)： 935263041118
廠商： NXP SEMICONDUCTORS
元件分類： 門電路
英文描述： AHC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
封裝： 4.40 MM, PLASTIC, SOT-402-1, TSSOP-14
文件頁(yè)數(shù)： 9/16頁(yè)
文件大小： 73K
代理商： 935263041118
1999 Sep 27
2
Philips Semiconductors
Product specication
Hex inverter
74AHC04; 74AHCT04
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Balanced propagation delays
Inputs accepts voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT04 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT04 provide six
inverting buffers.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT nA
OUTPUT nY
LH
HL
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation
delay nA to nY
CL =15pF;
VCC =5V
3.0
ns
CI
input
capacitance
VI =VCC or GND
4.0
pF
CPD
power dissipation
capacitance
CL =50pF;
f = 1 MHz;
notes 1 and 2
13.5
13.9
pF
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
1A to 6A
data inputs
2, 4, 6, 8, 10 and 12
1Y to 6Y
data outputs
7
GND
ground (0 V)
14
VCC
DC supply voltage
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