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參數(shù)資料
| 型號： | 935262922557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁數(shù)： | 92/147頁 |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922557 |
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1998 Apr 09
49
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
114
VF2
12
R
Video FIFO 2 underow/overow: this bit is set when the video FIFO 2
has an overow/underow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
VF1
11
R
Video FIFO 1 overow: this bit is set when the video FIFO 1 has an
overow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
AF2_in
10
R
Audio input FIFO 2 underow: this bit is set when the audio input
FIFO 2 has an underow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF2_out
9
R
Audio output FIFO 2 overow: this bit is set when the audio output
FIFO 2 has an overow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF1_in
8
R
Audio input FIFO 1 underow: this bit is set when the audio input
FIFO 1 has an underow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF1_out
7
R
Audio output FIFO 1 overow: this bit is set when the audio output
FIFO 1 has an overow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
6
reserved
VGT
5
R
Vertical Gate: this bit reects the vertical gate at the HPS output
LNQG
4
R
Line Qualier Gate: this bit reects the horizontal gate at the HPS
output
EC5S
3
R
Event Counter 5 Status: this bit is set when the event counter 5
exceeds its threshold. This bit is reset by writing a logic 1 to the ECS bit
in the ISR.
EC4S
2
R
Event Counter 4 Status: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
EC2S
1
R
Event Counter 2 Status: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
EC1S
0
R
Event Counter 1 Status: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
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