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參數(shù)資料
| 型號(hào)： | 935262900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | 935262900112 |
Philips Semiconductors
Product specification
PCK857
50–150 MHz differential 1:10 SDRAM clock driver
2
2000 June 15
853-2199 23880
FEATURES
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
1-to-10 differential clock distribution
Very low skew (< 100 ps) and jitter (< 100 ps)
3 V AV
CC and 2.5 V VCC
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16857 and
CBT3857
DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
GND
Y0
VCC
Y1
GND
Y2
GND
Y2
VCC
CLK
VCC
AVCC
AGND
GND
Y3
VCC
Y4
GND
Y5
VCC
Y6
GND
Y7
VCC
G
FBIN
VCC
FBOUT
GND
Y8
VCC
Y9
SW00358
GND
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DRAWING NUMBER
48-Pin Plastic TSSOP
0
°C to +85°C
PCK857 DGG
SOT362-1
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