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參數(shù)資料
| 型號： | 935262544112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 16 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 595K |
| 代理商： | 935262544112 |
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Product Information
74ALVCH16543;
16-bit D-type
registered
transceiver; 3-state
Information as of 2001-11-09
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Blockdiagram
Parametrics
Description
The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary
storage of the data flow in either direction.
Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each register to permit
independent control in either direction of the data flow.
The ‘16543’ contains two sections each consisting of two sets of eight D-type latches with separate inputs and controls for each
set. For data flow from A to B, for example, the A-to-B enable (nEAB, where n equals 1 or 2) inputs must be LOW in order to
enter data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function table. With nEAB LOW, a LOW signal
on the A-to-B latch enable (nLEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the
nLEAB signal stores the A data into the latches. With nEAB and nOEAB both LOW, the 3-state B output buffers are active and
Philips Semiconductors; 74ALVCH16543; 16-bit D-type registered transceiver; 3-state
file:///G|/imaging/BITTING/mail_pdf/cpl_rework/74alvch16543dgg.html (1 of 3) [1/9/2002 11:46:33 AM]
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