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參數(shù)資料
| 型號： | 935262466112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDSO14 |
| 封裝： | PLASTIC, SOT-402, 14 PIN |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 41K |
| 代理商： | 935262466112 |
December 1990
5
Philips Semiconductors
Product specication
7-stage binary ripple counter
74HC/HCT4024
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +125 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
CP to Q0
47
17
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
MR to Q0
63
23
18
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
Qn to Qn+1
25
9
7
80
16
14
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
master reset pulse width
HIGH
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
trem
removal time
MR to CP
50
10
9
6
2
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.6
fmax
maximum clock pulse
frequency
6.0
30
35
27
82
98
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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