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參數(shù)資料
| 型號： | 935262449118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AH, SOT-341-1, SSOP-28 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 935262449118 |
Philips Semiconductors
Product specification
PCK2001M
14.318–150 MHz I2C 1:10 clock buffer
2000 May 17
7
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = 0°C to +70°C
UNIT
NOTES
MIN
TYP9
MAX
TSDKP
SDRAM CLK period
1, 6
15.0
15.2
15.5
TSDKH
SDRAM CLK HIGH time
66 MHz
2, 6, 8
5.6
7.8
8.4
ns
TSDKL
SDRAM CLK LOW time
3, 6, 8
5.3
7.4
8.0
TSDKP
SDRAM CLK period
1, 6
10.0
10.01
10.5
TSDKH
SDRAM CLK HIGH time
100 MHz
2, 6, 8
3.3
5.1
5.7
ns
TSDKL
SDRAM CLK LOW time
3, 6, 8
3.1
4.9
5.5
TSDKP
SDRAM CLK period
1, 6
7.4
7.5
7.7
TSDKH
SDRAM CLK HIGH time
133 MHz
2, 6, 8
2.6
3.2
3.8
ns
TSDKL
SDRAM CLK LOW time
3, 6, 8
2.1
2.8
3.5
TSDRISE
SDRAM rise time
4, 6, 10
1.5
2.0
4.0
V/ns
TSDFALL
SDRAM fall time
4, 6, 11
1.5
2.9
4.0
V/ns
TPLH
SDRAM buffer LH propagation delay
6, 7
1.0
2.5
3.5
ns
TPHL
SDRAM buffer HL propagation delay
6, 7
1.0
2.5
3.5
ns
TPZL, TPZH
SDRAM buffer enable time
6, 7
1.0
2.6
5.0
ns
TPLZ, TPHZ
SDRAM buffer disable time
6, 7
1.0
2.7
5.0
ns
DUTY CYCLE
Output Duty Cycle
Measured at 1.5 V
5, 6, 7
45
52
55
%
TSDSKW
SDRAM Bus CLK skew
1, 6
150
250
ps
TDDSKW
Device to device skew
250
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5 V.
2. TSDKH is measured at 2.4 V as shown in Figure 3.
3. TSDKL is measured at 0.4 V as shown in Figure 3.
4. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at VCC = 3.3 V and Tamb = 25°C.
10. Typical is measured with MAX (30 pf) discrete load.
11. Typical is measured with MIN (20 pf) discrete load.
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