參數(shù)資料
型號(hào)： 935262385518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 30 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 X 1.40 MM, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 36/55頁(yè)
文件大?。?/td> 318K
代理商： 935262385518
Philips Semiconductors
Preliminary specification
XA-S3
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
2000 Mar 09
41
AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
Address Cycle
tCHLH
26
CLKOUT rising edge to ALE rising edge
–
15
ns
tCLLL
26
CLKOUT falling edge to ALE falling edge
–
11
ns
tCHAV
26
CLKOUT rising edge to address valid
–
29
ns
tCHAX
26
CLKOUT rising edge to address changing (hold time)
2
–
ns
Code Read Cycle
tCHPL
26
CLKOUT rising edge to PSEN asserted
–
16
ns
tCHPH
26
CLKOUT rising edge to PSEN de-asserted
–
15
ns
tIVCH
26
Instruction valid to CLKOUT rising edge (setup time)
30
–
ns
tCHIX
26
CLKOUT rising edge to instruction changing (hold time)
0
–
ns
tCHIZ
26
CLKOUT rising edge to Bus 3-State (code read)
–
tC–8
ns
Data Read Cycle
tCHRL
28
CLKOUT rising edge to RD asserted
–
20
ns
tCHRH
28
CLKOUT rising edge to RD de-asserted
–
16
ns
tDVCH
28
Data valid to CLKOUT rising edge (setup time)
28
–
ns
tCHDX
28
CLKOUT rising edge to Data changing (hold time)
0
–
ns
tCHDZ
28
CLKOUT rising edge to Bus 3-State (data read)
–
tC–8
ns
Data Write Cycle
tCHWL
30
CLKOUT falling edge to WR asserted
–
19
ns
tCHWH
30
CLKOUT rising edge to WR de-asserted
–
16
ns
tQVCH
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
tCHQX
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
Wait Input
tCHWTH
31
WAIT valid prior to CLKOUT rising edge8
30
4
ns
NOTES:
1. Load capacitance for all outputs = 50 pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to
the
XA User Guide for details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the
ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2)
This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
–
For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
–
For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if
CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2.
Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.
V3)
This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and
5 if CRA1/0 = 11).
V4)
This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and
CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11.
V5)
This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and
DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
V6)
This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and
DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and
5 if DRA1/0 = 11).
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