參數(shù)資料
型號(hào)： 935262073551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 36/43頁(yè)
文件大小： 206K
代理商： 935262073551
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TDA8006
Information as of 2000-08-20
TDA8006; Multiprotocol IC Card coupler
It is assumed that the reader of this data sheet is familiar with ISO 7816.
The TDA8006 is controlled either through a standard serial interface or a parallel bus, it takes care of all ISO 7816, EMV and GSM11.11
requirements. It gives the card and the set a very high level of security due to its special hardware against ESD, short circuit, power failure,
etc. Its integrated step-up converter allows operation within a supply voltage range of 4.2 to 6 V.
A special version of the TDA8006 is available which has its internal connections to the controller accessible through external pins. This
allows easy development and evaluation when used with a 80CL580 microcontroller or a development tool. An emulation board is available.
A software library has been developed, taking care of all actions required for T = 0, T = 1 and synchronous protocols. This library may be
either linked with the application software before masking, or masked in the internal ROM.
l
80C52 core with 16 kbyte ROM and 256 byte RAM
l
Extra 1 kbyte RAM outside the core for data storage
l
Control and communication through a standard RS232 full duplex interface or a parallel interface
l
Specific ISO 7816 UART with parallel access on I/O for automatic convention processing, variable baud rate through frequency or
division ratio programming, error management at character level for T = 0, extra guard time register
l
V
CC generation (5 V ±5% or 3 V ±5%, 65 mA maximum with controlled rise and fall times)
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Card clock generation (up to 10 MHz) with two times synchronous frequency doubling
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Card clock STOP HIGH, clock STOP LOW or 1.25 MHz (from internal oscillator) for card power-down mode
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CLKOUT output for clocking external devices with either f
xtal, 1/2 fxtal or 1/4 fxtal
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Automatic activation and deactivation sequence through an independent sequencer
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