參數(shù)資料
型號： 935261351112
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PDIP32
封裝： 0.400 INCH, PLASTIC, SOT-232, SDIP-32
文件頁數(shù)： 19/47頁
文件大?。?/td> 390K
代理商： 935261351112
1996 Jan 17
26
Philips Semiconductors
Preliminary specication
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
TDA9144
Horizontal section
CLP OUTPUT (OPB/CLP MODE); HA OUTPUT (LLC/HA) MODE (BOTH ON PIN 17)
VOH
HIGH level output voltage
4.0
5
5.5
V
VOL
LOW level output voltage
0.2
0.4
V
Isink
sink current
2
mA
Isource
source current
2
mA
tW(HA)
HA pulse width (32 LLC pulses)
4.65
s
td
delay between middle of horizontal
sync pulse and middle of HA
note 4
0.3
0.45
0.6
s
tW
CLP pulse width (25 LLC pulses)
3.65
s
td
delay start CLP pulse to start black
set-up (33 LLC pulses + Y delay)
HD = 1 or MACP = 1; YD3 to
YD0 = 1011; see Fig.5
5.35
s
td
delay between middle of horizontal
sync pulse and start of CLP pulse
note 4
3.0
3.2
3.4
s
σ
6
σ jitter
1 in auto mode
5ns
FIRST LOOP (
1)
f
frequency deviation when not locked
1.5
%
VCC
supply voltage dependence
40
Hz/V
fCR
catching range
±625
Hz
fHR
holding range
±1.0
kHz
φ
static phase shift
0.1
s/kHz
LLC OUTPUT (PIN 16); LLC/HA MODE
fo
output frequency
440
× f
H
50 Hz standard
6.875
MHz
440
× f
H
60 Hz standard
6.923
MHz
Vo(p-p)
output amplitude
(peak-to-peak value)
0.25
V
Vo
DC output voltage level
2.5
V
td
delay between negative edge of LLC
and positive edge of HA pulse
CL = 15 pF
102040ns
Vertical section
VERTICAL OSCILLATOR
ffr
free running frequency
FORF = 1; divider ratio 628
50
Hz
FORF = 0; divider ratio 528
60
Hz
fLR
frequency locking range
43
64
Hz
LR
divider locking range
488
625
722
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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