
1999 Oct 06
6
Philips Semiconductors
Preliminary specication
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
CHARACTERISTICS
VCCA =V7 to V6 = 2.7 to 3.6 V; VCCD =V10 to V9 = 2.7 to 3.6 V; VCCO =V20 (or V22) to V19 (or V21) = 2.7 to 3.6 V;
AGND to DGND and OGND shorted together; VCCA to VCCD = 0.15 to +0.15 V; VCCD to VCCO = 0.15 to +0.15 V;
VCCA to VCCO = 0.15 to +0.15 V; Tamb = 0 to 70 °C; typical values measured at VCCA =VCCD =VCCO = 3.0 V and
Tamb =25 °C; single-ended input; unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
output stages supply voltage
2.7
3.0
3.6
V
ICCA
analog supply current
32
40
48
mA
ICCD
digital supply current
13
16
22
mA
ICCO
output stages supply current
fi = ramp input
0.1
tbf
mA
fi = 20 MHz
4
tbf
mA
Internal reference (pin SDN); note 1
Vref
reference voltage
1.21
1.25
1.29
V
Vreg
line regulation voltage
2.7 < VCCA < 3.6 V
0.4
3
mV
TC
temperature coefcient
18
ppm/K
IL
load current
1
mA
Internal reference (pin REFOUT)
Vo(ref)
reference voltage
1.76
1.82
1.88
V
Vo(reg)
line regulation voltage
2.7 < VCCA < 3.6 V
1.5
4
mV
TC
temperature coefcient
18
ppm/K
IL
load current
1
mA
Adjustable full scale input (pin REFIN); see Figs 3, 4, and 7
Iref
input current
VREFIN = 1.25 V
0.87
mA
Clock input (pin CLK); note 2
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2
VCCD
V
IIL
LOW-level input current
VCLK =0
2
+2
A
IIH
HIGH-level input current
VCLK =VCCD
5
A
tr
clock rise time
0.75
tbf
ns
tf
clock fall time
0.75
tbf
ns
Zi
input impedance
fCLK = 100 MHz
32
k
Ci
input capacitance
fCLK = 100 MHz
2
pF
Standby input (pin STDBY); see Table 1
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2
VCCD
V
IIL
LOW-level input current
VSTDBY =0
5
A
IIH
HIGH-level input current
VSTDBY =VCCD
5
A