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參數(shù)資料
| 型號： | 935261327557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 262K |
| 代理商： | 935261327557 |
1999 Sep 16
12
Philips Semiconductors
Objective specication
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
NOISE
Vn(o)(rms)
output referred noise
(RMS value)
DPGA at G(max);
Zi =50 ; noise
bandwidth = 15 MHz
tbf
2
mVrms
ADC (without DPGA; fCLK = 100 MHz; from buffer input to digital output)
ANALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N)
Vi(dif)(FS)(p-p)
differential input voltage
full-scale amplitude;
(peak-to-peak value)
500
mV
Vi(cm)(ADC)
common mode input voltage
tbf
V
Ii(ADC)
input current
at Vi(cm)(ADC)
tbf
A
Ri(ADC)
input resistance
20
k
Ci(ADC)
input capacitance
3
pF
STATIC LINEARITY
NLdc(i)
DC integral non-linearity
ramp input;
without DPGA
±1.0
tbf
LSB
with DPGA
at G(min)
±3.0
tbf
LSB
NLdc(dif)
DC differential non-linearity
ramp input;
without DPGA
±0.5
tbf
LSB
with DPGA
at G(min)
±0.5
tbf
LSB
DYNAMIC PERFORMANCE
THD
total harmonic distortion
fi = 4.43 MHz
55
dB
S/N
signal-to-noise ratio
without harmonics
46
dB
BANDWIDTH
B(3dB)(ADC)
ADC
3 dB analog bandwidth
120
MHz
CROSSTALK BETWEEN ADC1 AND ADC2
α
ct
crosstalk between channels
40
dB
CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1
VIL
LOW-level clock input voltage
0.8
V
VIH
HIGH-level clock input voltage
2.0
VDDD
V
IIH
HIGH-level clock input current
100
A
IIL
LOW-level clock input current
100
A
DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR)
VIL
LOW-level input voltage
0.8
V
VIH
HIGH-level input voltage
2.0
VDDD
V
IIH
HIGH-level input current
5
+5
A
IIL
LOW-level input current
5
+5
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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