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參數(shù)資料
| 型號(hào)： | 935261296529 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PEDESTAL, PLASTIC, MO-047, SOT-188-3, LCC-68 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 303K |
| 代理商： | 935261296529 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
28
Table 34.
GRxFIFO - Global RxFIFO Register
Bits 7:0
8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data
The RxFIFO of the channel indicated in the CIR channel field.
Undefined when the CIR interrupt context is not a receiver interrupt.
Global TxFIFO Register
Table 35.
GTxFIFO - Global TxFIFO Register
Bits 7:0
8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data
The TxFIFO of the channel indicated in the CIR channel field.
Undefined when the CIR interrupt context is not a transmitter
interrupt. Writing to the GTxFIFO when the current interrupt is not a
transmitter event may result in the characters being transmitted on a
different channel than intended.
Table 36.
IPR - Input Port Register
Bit 7
Bit 6
Bit 7
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
I/O3
change
I/O2
change
I/O1
change
I/O0
change
I/O3
state
I/O2
state
I/O1
state
I/O0
state
0 - no change
1 - change
0 - no change
1 - change
0 - no change
1 - change
0 - no change
1 - change
The actual logic level at the I/O pin.
1 = high level; 0 =- low level.
This register may be read to determine the current level of the I/O pins and examine the output of the change detectors assigned to each pin. If
the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.
Table 37.
I/OPIOR - I/O Port Interrupt and Output Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O3 enable
I/O2 enable
I/O1 enable
I/O0 enable
I/O3 output
I/O2 output
I/O1 output
I/O0 output
0 - disable
1 - enable
0 - disable
1 - enable
0 - disable
1 - enable
0 - disable
1 - enable
OPR[3]
OPR[2]
OPR[1]
OPR[0]
I/OPIOR[7:4] bits activate the input change of state detectors. If a pin is configured as an output, a b’1 value written to a I/O field has no effect.
I/OPIOR[3:0] bits hold the datum which is the inverse of the datum driven to its associated I/O pin when the I/OPCR control bits for that pin are
programmed to b’01.
Table 38.
I/OPCR - I/O Port Configuration Register
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
I/O3 control
I/O2 control
I/O1 control
I/O0 control
00 - GPI/TxC input
01 - I/OPIOR[3] output
10 - TxC16x output
11 - TxC1x output
00 - GPI/RxC input
01 - I/OPIOR[2]/RTSN *
10 - RxC1x output
11 - RxC16x output
00 - GPI input
01 - I/OPIOR[1]/RTSN *
10 - Reserved
11 - RxC1x output
00 - GPI/CTSN input
01 - I/OPIOR[0]output
10 - TxC1x output
11 - TxC16x output
* If I/OPCR(5:4) is programmed as ’01’ then the RTSN functionality is assigned to I/O2, otherwise, this function can be implemented on I/O1.
(This allows for a lower pin count package option.)
This register contains 4, 2 bit fields that set the direction and source for each of the I/O pins associated with the channel. The I/O2 output may
be RTSN if MR1[7] is set, or may signal “end of transmission” if MR2[5] is set.(Please see the descriptions of these functions under the MR1
and MR2 register descriptions) If this control bit is cleared, the pin will use the OPR[2] as a source if I/OPCR[5:4] is b’01. The b’00 combinations
are always inputs. This register resets to x’0, effectively configuring all I/O pins as inputs on power up or reset. Inputs may be used as RxC, TxC
inputs or CTSN and General Purpose Inputs simultaneously. All I/O ports are equipped with change detectors that may be used to generate
interrupts or can be polled, as required.
NOTE: To ensure that CTSN, RTSN and an external RxC are always available, if I/O2 is not selected as the RTSN output, the RTSN function is
automatically provided on I/O1.
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