參數(shù)資料
型號： 935261296518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PEDESTAL, PLASTIC, MO-047, SOT-188-3, LCC-68
文件頁數(shù)： 28/52頁
文件大?。?/td> 303K
代理商： 935261296518
Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
34
Table 46.
Register Map, Data
A(7:0)
UART A
A(7:0)
Read
Write
1000 0000 (x80)
Mode Register a (MR2a)
Mode Register a (MR2a)
1000 0001 (x81)
Status Register a (SRa)
Command Register a (CRa)
1000 0010 (x82)
Interrupt Status Register a (ISRa)
Interrupt Mask Register a (IMRa)
1000 0011 (x83)
Receiver FIFO Reg a (RxFIFOa)
Transmitter FIFO Reg a (TxFIFOa)
1000 0100 (x84)
Reserved
BRG Timer Reg Upper a (BRGTRUa)
1000 0100 (x84)
Input Port Reg a (IPRa)
Reserved
1000 0101 (x85)
I/O Port Interrupt and Output a I/OPIORa)
I/O Port Interrupt and Output a (I/OPIORa)
1000 0110 (x86)
Xon/Xoff Interrupt Status Reg a (XISRa)
Reserved
1000 0111 (x87)
GP Out Select Reg (GPOSR)
GP Out Select Reg (GPOSR)
1000 1011 (x8B)
GP Out Clk Reg (GPOC)
GP Out Clk Reg (GPOC)
1000 1100 (x8C)
Current Interrupt Reg (CIR)
Update CIR
1000 1101 (x8D)
Reserved
BRG Timer Reg Upper b (BRGTRUb)
1000 1110 (x8E)
Global Receive FIFO Reg (GRxFIFO)
Global Transmit FIFO Reg (GTxFIFO)
1000 1111 (x8F)
Global Chip Configuration Reg (GCCR)
Global Chip Configuration Reg (GCCR)
A(7:0)
UART B
A(7:0)
Read
Write
1001 0000 (x90)
Mode Register b (MR2b)
Mode Register b (MR2b)
1001 0001 (x91)
Status Register b (SRb)
Command Register b (CRb)
1001 0010 (x92)
Interrupt Status Register b (ISRb)
Interrupt Mask Register b (IMRb)
1001 0011 (x93)
Receiver FIFO Reg b (RxFIFOb)
Transmitter FIFO Reg b (TxFIFOb)
1001 0100 (x94)
Reserved
BRG Timer Reg Lower a (BRGTRLa)
1001 0100 (x94)
Input Port Reg b (IPRb)
Reserved
1001 0101 (x95)
I/O Port Interrupt and Output b (I/OPIORb)
I/O Port Interrupt and Output b (I/OPIORb)
1001 0110 (x96)
Xon/Xoff Interrupt Status Reg b (XISRb)
Reserved
1001 0111 (x97)
GP Output Reg (GPOR)
GP Output Reg (GPOR)
1001 1010 (x9A)
Reserved
Reserved
1001 1011 (x9B)
GP Out Data Reg (GPOD)
GP Out Data Reg (GPOD)
1001 1100 (x9C)
Reserved
BRG Timer Control Reg (BRGCTCR)
1001 1100 (x9C)
Global Interrupt Channel Reg (GICR)
Reserved
1001 1101 (x9D)
Reserved
BRG Timer Reg Lower b (BRGTRLb)
1001 1101 (x9D)
Global Interrupt Byte Count (GIBCR)
Reserved
1001 1110 (x9E)
Reserved
Reserved
1001 1111 (x9F)
Global Interrupt Type Register (GITR)
Reserved
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