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參數(shù)資料
| 型號： | 935261296512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PEDESTAL, PLASTIC, MO-047, SOT-188-3, LCC-68 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大?。?/td> | 303K |
| 代理商： | 935261296512 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
4
Pin Description
MNEMONIC
TYPE
DESCRIPTION
SClk
I
Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater than
twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
CEN
I
Chip select: Active low. When asserted, allows I/O access to QUART registers by host CPU. W_RN signal
indicates direction. (Must not be active in IACKN cycle)
A(7:0)
I
Address lines (A[6] is NOT used. See “Host Interface” )
D(7:0)
I/O
8-bit bi-directional data bus. Carries command and status information between 28L194 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 28L194
W_RN
I
Write Read not control: When high indicates that the host CPU will write to a 28L194 register or transmit FIFO.
When low, indicates a read cycle. 0 = Read; 1 = Write
DACKN
O
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
Open drain requires a pull-up device.
IRQN
O
Interrupt Request: Active low. When asserted, indicates that the 28L194 requires service for pending
interrupt(s). Open drain requires a pull-up device.
IACKN
I
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt
acknowledge cycle. (Do not use CEN in an IACKN cycle)
TD(a-d)
O
Transmit Data: Serial outputs from the 4 UARTs.
RD(a-d)
I
Receive Data: Serial inputs to the 4 UARTs
I/O0(a-d)
I/O
Input/Output 0: Multi-use input or output pin for the UART.
I/O1(a-d)
I/O
Input/Output 1: Multi-use input or output pin for the UART.
I/O2(a-d)
I/O
Input/Output 2: Multi-use input or output pin for the UART.
I/O3(a-d)
I/O
Input/Output 3: Multi-use input or output pin for the UART.
Gin(1:0)
I
Global general purpose inputs, available to any/all channels.
Gout(1:0)
O
Global general purpose outputs, available from any channel.
RESETN
I
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and
restart the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.
X1/CCLK
I
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2-8 MHz crystal. It may
alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
X2
O
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
must be left unconnected.
Power Supplies
I
16 pins total 8 pins for Vss, 8 pins for Vcc
NOTE:
1. Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf). These edges may move as fast as 1 to 3 ns fall
or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATING
UNIT
Tamb
Operating ambient temperature range2
See Note 3
°C
Tstg
Storage temperature range
-65 to +150
°C
VCC
Voltage from VDD to VSS4
-0.5 to +7.0
V
VSS
Voltage from any pin to VSS
-0.5 to VCC + 0.5
V
PD
Package Power Dissipation (PLCC)
2.87
W
PD
Package Power Dissipation (LQFP)
2
W
Derating factor above 25
°C (PLCC package)
23
mW/
°C
Derating factor above 25
°C (LQFP package)
16
mW/
°C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
2. For operating at elevated temperatures, the device must be derated based on +150
°C maximum junction temperature.
3. Parameters are valid over specified temperature range. See Ordering Information table for applicable temperature range and operating
supply range.
4. This product includes circuitry specifically designed for the protewction of its internal devices from damaging effects of excessive static
charge.
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