參數(shù)資料
型號(hào)： 935261155112
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： 0.400 INCH, PLASTIC, SOT-232, DIP-32
文件頁(yè)數(shù)： 27/63頁(yè)
文件大?。?/td> 293K
代理商： 935261155112
1999 Jul 13
33
Philips Semiconductors
Product specication
I2C-bus autosync deection controllers for
PC/TV monitors
TDA4853; TDA4854
I2C-BUS PROTOCOL
I2C-bus data format
Notes
1. S = START condition.
2. SLAVE ADDRESS (MAD) = 1000 1100.
3. A = acknowledge, generated by the slave. No acknowledge, if the supply voltage is below 8.3 V for start-up and 8.1 V
for shut-down procedure.
4. SUBADDRESS (SAD).
5. DATA, if more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed.
6. P = STOP condition.
It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 and 5 V applications
(reference level = 1.8 V). Default register values after power-up are random. All registers have to be preset via software
before the soft start is enabled.
Important: If the register contents are changed during the vertical scan, this might result in a visible interference on the
screen. The cause for this interference is the abrupt change in picture geometry which takes effect at random locations
within the visible picture.
To avoid this kind of interference, the adjustment of the critical geometry parameters HSIZE, HPOS, VSIZE and VPOS
should be synchronized with the vertical flyback. This should be done in such a way that the adjustment change takes
effect during the vertical blanking time (see Fig.19).
For very slow I2C-bus interfaces, it might be necessary to delay the transmission of the last byte (or only the last bit) of
an I2C-bus message until the start of the vertical sync or vertical blanking.
S(1)
SLAVE ADDRESS(2)
A(3)
SUBADDRESS(4)
A(3)
DATA(5)
A(3)
P(6)
Fig.19 Timing of the I2C-bus transmission for interference-free adjustment.
handbook, full pagewidth
MGM088
vertical
sync pulse
vertical
blanking pulse
SDA
parameter change takes effect
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