
1999
Sep
27
5
Philips
Semiconductors
Preliminar
y
specication
Digital
PC-camer
a
signal
processor
SAA8113HL
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6
BLOCK
DIA
GRAM
b
ook,
full
pagewidth
FCE312
MICRO-
CONTROLLER
80C51
SAA8113HL
INTERNAL
MICRO-
CONTROLLER
INTERFACE
ANALOG
OUTPUT
(PRE-
PROCESSING)
PAL/NTSC
ENCODER
P1
P2
AUDIO BUFFER
VDAC
P0
P4
P3
5, 6, 7, 8
11
SDAE
15
SDA
14
SCL
DISPLAY
UV
PROCESSING
RGB
TO
UV
RGB
PROCESSING
Y
AND
CR, CB
SEPARATION
OFFSET
PRE-
PROCESSING
Y
PROCESSING
10
SCLE
85 to 94
MODE
CONTROL
AND
CLOCK
GENERATOR
1 to 3
28
3
9
2
8
7
4
2
4
63
8
3
10
62
63
59
58
50
ALE
49 to 42
P0.7 to P0.0
39 to 33
AD14 to AD8
KNOB3
to
KNOB0
CCD9
to
CCD0
M2 to M0
32
PSEN
22
18
27
26, 28
29
VDDA4
24, 25
55, 96
VDDD1,
VDDD2
13, 17, 23,
40, 57, 64, 71, 83
54, 56, 95
12, 19, 20, 21,
41, 60, 61, 72, 82
AGND5,
AGND6
MICIAB,
VCOMAB
VDDA1 to VDDA3,
VDDA5 to VDDA9
DGND1 to DGND3
AGND1 to AGND4,
AGND7 to AGND11
OUTAB
XOSC
XIN
XOUT
CDACOUT
RBIASCDAC
MISCELLANEOUS
FUNCTIONS
PPG
SENSOR/PREPROCESSOR TIMING AND CONTROL
VH
REFERENCE
TIMING
MEASUREMENT ENGINE
CDAC
4
16, 53
KNOB4
9
RESET
52
EA
100, 99,
98, 97,
84, 51,
30, 31
SDATA,
SCLK,
STROBE,
STDBY,
SMP,
LED,
OUTBVEN,
OUTGAIN
65, 66,
67, 68,
69, 70
V1X,
VH1X,
V2X,
V3X,
VH3X,
V4X
75,
74, 76
FH1,
FH2,
FR
73
OFDX
79, 80,
77, 78
BCP,
DCP,
FS,
FCDS
81
T1,
INT1
CLK1
VDOBCVBS
DECREF
Fig.1 Block diagram.