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參數(shù)資料
| 型號： | 935260900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 935260900112 |
2002 Mar 15
2
Philips Semiconductors
Product specication
Quad 2-input multiplexer
74LVC157A
FEATURES
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC157A is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC157A is a quad 2-input multiplexer which select
four bits of data from two sources under the control of a
common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable
input (E) is active LOW. When E is HIGH, all of the outputs
(1Y to 4Y) are forced LOW regardless of all the other input
conditions. Moving the data from two groups of registers to
four common output buses is a common use of the
74LVC157A. The state of the common data select
input (S) determines the particular register from which the
data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic
by generating any 4 of the 16 different functions of two
variables with one variable common.
The 74LVC157A is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
nI0,nI1 to nY
CL = 50 pF; VCC = 3.3 V
2.6
ns
EtonY
CL = 50 pF; VCC = 3.3 V
2.8
ns
StonY
CL = 50 pF; VCC = 3.3 V
2.6
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per gate
VCC = 3.3 V; notes 1 and 2
15
pF
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