參數(shù)資料
型號(hào)： 935260767112
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： PLASTIC, SOT-341, SSOP-28
文件頁數(shù)： 36/44頁
文件大?。?/td> 241K
代理商： 935260767112
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TDA6402; TDA6402A;
TDA6403; TDA6403A
TDA6402; TDA6402A;
TDA6403; TDA6403A
Information as of 2000-08-23
TDA6402; TDA6402A; TDA6403; TDA6403A; 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
The TDA6402, TDA6402A, TDA6403 and TDA6403A are programmable 2-band mixers/oscillators and synthesizers intended for VHF/UHF
cable tuners.
The devices include two double balanced mixers and two oscillators for the VHF and UHF band respectively, an IF amplifier and a PLL
synthesizer. The VHF band can be split-up into two sub-bands using a proper oscillator application and a switchable inductor. Two pins are
available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling. Four PNP ports are
provided. Band selection is provided by using pin PUHF. When PUHF is ‘ON’, the UHF mixer-oscillator is active and the VHF band is
switched off. When PUHF is ‘OFF’, the VHF mixer-oscillator is active and the UHF band is ‘OFF’. PVHFL and PVHFH are used to select
the VHF sub-bands. FMST is a general purpose port, that can be used to switch an FM sound trap. When it is used, the sum of the
collector currents has to be limited to 30 mA.
The synthesizer consists of a divide-by-eight prescaler, a 15-bit programmable divider, a crystal oscillator and its programmable reference
divider and a phase/frequency detector combined with a charge pump which drives the tuning amplifier, including 33 V output (V33) at pin
VT.
Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 7.8125 kHz, 6.25 kHz or 3.90625 kHz with
a 4 MHz crystal.
The device can be controlled according to the IC-bus format or 3-wire bus format depending on the voltage applied to pin SW . In the 3-
wire bus mode (SW = HIGH), pin LOCK/ADC is the LOCK output.
The LOCK output is LOW when the PLL loop is locked. In the IC-bus mode (SW = LOW), the lock detector bit FL is set to logic 1 when the
loop is locked and is read on the SDA line (Status Byte; SB) during a READ operation in IC-bus mode only. The Analog-to-Digital
Converter (ADC) input is available on pin LOCK/ADC for digital AFC control in the IC-bus mode only. The ADC code is read during a
READ operation on the IC-bus . In test mode, pin LOCK/ADC is used as a TEST output for f
REF and 1/2 fDIV, in both IC-bus mode and 3-
wire bus mode .
When the automatic charge pump current switch mode is activated and when the loop is phase-locked, the charge pump current value is
automatically switched to LOW. This action is taken to improve the carrier-to-noise ratio.
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Description
相關(guān)PDF資料
PDF描述
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