
1999 Jun 15
2
Philips Semiconductors
Product specication
Octal dual supply translating transceiver; 3-state
74LVC4245A
FEATURES
In accordance with JEDEC
standard no. 8-1A
Wide supply voltage range:
3 V port: 1.5 to 3.6 V
5 V port: 1.5 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs accept voltages up
to 5.5 V.
DESCRIPTION
The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74LVC4245A is an octal dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive
directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V
supply environment.
The 74LVC4245A features an output enable (OE) input for easy cascading and
a send/receive (DIR) input for direction control. (OE) controls the outputs so
that the buses are effectively isolated.
In suspend mode, when VCCA is zero, there will be no current flow from one
supply to the other supply. The A-outputs must be set 3-state and the voltage
on the A-bus must be smaller than Vdiode (typ. 0.7 V). VCCA ≥ VCCB (except in
suspend mode).
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
CL =50pF
An to Bn
VCCA = 5.0 V
4.0
ns
Bn to An
VCCB = 3.3 V
4.0
ns
CI/O
input/output capacitance
10.0
pF
CPDA
A port
An to Bn
VI = GND to VCC; note 1
7.8
pF
Bn to An
VI = GND to VCC; note 1
27.9
pF
CPDB
B port
An to Bn
VI = GND to VCC; note 1
26
pF
Bn to An
VI = GND to VCC; note 1
10.4
pF