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參數(shù)資料
| 型號(hào)： | 935260746112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | 935260746112 |
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2002 Mar 12
2
Philips Semiconductors
Product specication
3-to-8 line decoder/demultiplexer; inverting
74LVC138A
FEATURES
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output drive capability 50 transmission lines at
125
°C
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC138A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC138A accepts three binary weighted address
inputs (A0,A1 and A2) and when enabled, provides 8
mutually exclusive active LOW outputs (Y0 to Y7).
The 74LVC138A features three enable inputs: two active
LOW (E1 and E2) and one active HIGH (E3). Every output
will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines)
decoder with just four 74LVC138A ICs and one inverter.
The 74LVC138A can be used as an eight output
demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied
to their appropriate active HIGH or LOW state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
CL = 50 pF; VCC = 3.3 V
An to Yn
3.5
ns
E3 to Yn, En to Yn
3.5
ns
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per package
VCC = 3.3 V; notes 1 and 2
21
pF
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| 935260747118 | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 935260747112 | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
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