
2000 Mar 08
20
Philips Semiconductors
Product specication
Digital video encoder
SAA7128H; SAA7129H
Table 16 Subaddress 3AH
Table 17 Subaddresses 42H to 44H and 48H to 4AH
Table 18 Subaddresses 45H to 47H and 4BH to 4DH
BIT
SYMBOL
DESCRIPTION
7
CBENB
0 = data from input ports is encoded; default state after reset
1 = colour bar with xed colours is encoded
6
These 2 bits are reserved; each must be set to a logic 0.
5
4
SYMP
0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of
“ITU-R BT.656” compatible data at
MPEG port
3
DEMOFF
0 = YCBCR-to-RGB dematrix is active; default state after reset
1=YCBCR-to-RGB dematrix is bypassed
2
CSYNC
0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC
1
MP2C
0 = input data is 2’s complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset
0
VP2C
0 = input data is 2’s complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset
ADDRESS
BYTE
DESCRIPTION
42H
48H
KEY1LU
KEY1UU
Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE1
× video signal + (1 FADE1) × MPEG signal
Default value of all bytes after reset = 80H.
43H
49H
KEY1LV
KEY1UV
44H
4AH
KEY1LY
KEY1UY
ADDRESS
BYTE
DESCRIPTION
45H
4BH
KEY2LU
KEY2UU
Key colour 2 lower and upper limits for U,V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE2
× video signal + (1 FADE2) × LUT values
Default value of all bytes after reset = 80H.
46H
4CH
KEY2LV
KEY2UV
47H
4DH
KEY2LY
KEY2UY