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參數(shù)資料
| 型號： | 935260348518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 205K |
| 代理商： | 935260348518 |
1999 Jan 06
8
Philips Semiconductors
Preliminary specication
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
Voltage controlled regulator input Vref (referenced to AGND); note 2
Vref
full-scale xed voltage
VCCA =5V
3.175
V
VI(p-p) VI(p-p) input voltage amplitude
(peak-to-peak value)
Vref =VCCA 1.825 V
2.0
V
Iref
input current at Vref
0.5
10
A
Outputs (referenced to OGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)
VOL
LOW-level output voltage
IOL =2mA
0
0.5
V
VOH
HIGH-level output voltage
IOH = 0.4 mA
VCCO 0.5
VCCO
V
Io
output current in 3-state
output level between 0.5 V
and VCCO
20
+20
A
Switching characteristics
CLOCK FREQUENCY fCLK; see Fig.5
fCLK(min)
minimum clock frequency
SH = HIGH
1
MHz
SH = LOW
1
kHz
fCLK(max)
maximum clock frequency
TDA8765H/4
40
MHz
TDA8765H/5
55
MHz
tCLKH
clock pulse width HIGH
8.5
ns
tCLKL
clock pulse width LOW
8.5
ns
Analog signal processing; 50% clock duty factor; VI VI = 2.0 V; Vref =VCCA 1.825 V; see Table 1
LINEARITY
INL
integral non-linearity
fCLK = 4 MHz; fi = 400 kHz
±0.5
±1.75
LSB
DNL
differential non-linearity
fCLK = 4 MHz; fi = 400 kHz;
no missing code
±0.3
±0.5
LSB
Eoffset
offset error
VCCA =VCCD =VCCO =5V;
Tamb =25 °C; VI = VI;
output code = 511
tbf
11
tbf
mV
EG
gain error amplitude; spread
from device to device
VCCA =VCCD =VCCO =5V;
Tamb =25 °C;
VI(p-p) VI(p-p) = 2.0 V
5
+5
%FS
BANDWIDTH (fCLK = 55 MHz); note 3
B
analog bandwidth
3 dB; full-scale input
tbf
200
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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