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參數(shù)資料
| 型號(hào)： | 935260018557 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-393, QFP-64 |
| 文件頁(yè)數(shù)： | 22/75頁(yè) |
| 文件大?。?/td> | 479K |
| 代理商： | 935260018557 |
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1998 May 15
29
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
Timing is compatible with SAA7110; I2C-bus bit FECO = 0.
handbook, full pagewidth
LLC
CREF
HREF
VPO
t
SU;DAT
t
HD;DAT
to 3-state
MGC657
from 3-state
t
OHD;DAT
t
PD
t
PDZ
FEI
Fig.20 Real time control output.
(1) Set to zero for one transmission, if a phase reset of the fsc DTO is applied via I2C-bus bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (fLFCO × 4=fLLC); 16 LSB from 20, upper four bits are fixed to 0100b.
Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits.
The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
Where: word length DTO1 = 24 bits.
f
LFCO
INCR
HPLL
f
XTAL
×
2
word length DTO2
-------------------------------------------------
=
f
sc
INCR
FSCPLL
f
XTAL
×
2
word length DTO1
-------------------------------------------------------
INCR
HPLL
2
19
----------------------------
×
=
handbook, full pagewidth
TIME SLOT:
BIT NO.:
transmitted once per line
22
1
21
19
20
15
16
17
18
7
8
9
11 10
12
13
14
SEQUENCE
19
0
67
2
3
6
4
5
2
3
0
16
45
RESERVED
16
INCRFSCPLL
MGC649
63
0
1
RESERVED
128
HIGH
LOW
15
INCRHPLL
RESERVED
1
68
DTO RESET(1)
50 Hz fields: 235
60 Hz fields: 232
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