參數(shù)資料
型號(hào)： 935260017551
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-314, LQFP-64
文件頁(yè)數(shù)： 56/75頁(yè)
文件大?。?/td> 479K
代理商： 935260017551
1998 May 15
6
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
7
PINNING
SYMBOL
PIN
I/O/P
DESCRIPTION
(L)QFP64
n.c.
1
Do not connect.
TDO
2
O
Test data output for boundary scan test; note 1.
TDI
3
I
Test data input for boundary scan test; note 1.
TMS
4
I
Test mode select input for boundary scan test or scan test; note 1.
VSSA2
5
P
Ground for analog supply voltage channel 2.
AI22
6
I
Analog input 22.
VDDA2
7
P
Positive supply voltage for analog channel 2 (+3.3 V).
AI21
8
I
Analog input 21.
VSSA1
9
P
Ground for analog supply voltage channel 1.
AI12
10
I
Analog input 12.
VDDA1
11
P
Positive supply voltage for analog channel 1 (+3.3 V).
AI11
12
I
Analog input 11.
VSSS
13
P
Substrate ground connection.
AOUT
14
O
Analog test output; for testing the analog input channels.
VDDA0
15
P
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).
VSSA0
16
P
Ground for internal CGC.
VREF
17
O
Vertical reference output signal (I2C-bit COMPO = 0) or inverse composite blanking
signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV).
VDDD5
18
P
Digital supply voltage 5 (+3.3 V).
VSSD5
19
P
Ground for digital supply voltage 5.
LLC
20
O
Line-locked system clock output (27 MHz).
LLC2
21
O
Line-locked clock 1
2 output (13.5 MHz).
CREF
22
O
Clock reference output: this is a clock qualier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualier) is
provided on this pin.
RES
23
O
Reset output (active LOW); sets the device into a dened state. All data outputs are
in high impedance state. The I2C-bus is reset (waiting for start condition).
CE
24
I
Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.
VDDD4
25
P
Digital supply voltage input 4 (+3.3 V).
VSSD4
26
P
Ground for digital supply voltage input 4.
HS
27
O
Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64
s) via I2C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC
increments can be performed via I2C-bus bits HDEL1 and HDEL0.
RTS1
28
O
Two functions output; controlled by I2C-bus bit RTSE1.
RTSE1 = 0: PAL line identier (LOW = PAL line); indicates the inverted and
non-inverted R
Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;
a high state indicates that the internal horizontal PLL has locked.
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