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參數(shù)資料
| 型號： | 935258960118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | Buffer和線驅(qū)動 |
| 英文描述： | LINE TRANSCEIVER, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 935258960118 |
Philips Semiconductors
Product data
PDIUSBP11A
Universal Serial Bus transceiver
2001 Jun 12
3
PIN DESCRIPTION
PIN
No.
PIN
SYMBOL
I/O
NAME AND FUNCTION
3
RCV
O
Receive data. CMOS level output for USB differential input
2
OE#
I
Output Enable. Active LOW, enables the transceiver to transmit data on the bus.
When not active the transceiver is in receive mode
1
MODE
I
Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and in this
mode, the PDIUSBP11A is backward compatible to PDIUSBP11. When connected to
GND, the VMO/FSEO pin takes the function of FSEO (Force SEO).
Inputs to differential driver. (Outputs from SIE).
MODE
VPO
VMO/FSEO
RESULT
0
Logic “0”
0
1
SE0#
12, 13
VPO,VMO/FSEO
I
1
0
Logic “1”
12, 13
VPO, VMO/FSEO
I
1
SEO#
1
0
SE0#
0
1
Logic “0”
1
0
Logic “1”
1
Illegal code
Gated version of D– and D+. Outputs are logic “0” and logic “1”. Used to detect single
ended zero (SE0#), error conditions, and interconnect speed. (Inputs to SIE).
VP
VM
RESULT
4, 5
VP, VM
O
0
SE0#
0
1
Low Speed
1
0
Full Speed
1
Error
11, 10
D+, D–
AI/O
Data+, Data–. Differential data bus conforming to the Universal Serial Bus standard.
6
SUSPND
I
Suspend. Enables a low power state while the USB bus is inactive. While the suspnd
pin is active it will drive the RCV pin to a logic “0” state. Both D+ and D– are tri-stated.
9
SPEED
I
Edge rate control. Logic “1” operates at edge rates for “full speed”. Logic “0” operates
edge rates for “l(fā)ow speed”.
14
VCC
3.0V to 3.6V power supply
7
GND
Ground reference
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