參數(shù)資料
型號: 935256670518
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
封裝: 12 X 12 X 1.40 MM, PLASTIC, LQFP-80
文件頁數(shù): 34/39頁
文件大?。?/td> 314K
代理商: 935256670518
1997 Jun 13
4
Philips Semiconductors
Preliminary specication
Digital Signal Processor (DSP) for
cameras
SAA8110G
BLOCK DIAGRAM
full pagewidth
MGK158
7
to
16
CCD9
to
CCD0
CLK1
V
DDD(C1)
V
DDD(C2)
V
DDD(C3)
V
DDD(P1)
V
DDD(P2)
V
SSD(C1)
V
SSD(C2)
V
SSD(C3)
V
SSD(C4)
V
SSD(P1)
V
SSD(P2)
V
DDA(BG)
V
DDA(DC)
V
DDA(CD)
V
DDA(O1)
V
DDA(O2)
V
DDA(O3)
V
SSA(CD)
V
SSA(OB)
V
SSA(BG)
1,
29,72,
46,
62
6,
17,
76,
78,
53,
71
45,
41,
22,
40,
38,
36
19,
34,
42
OFFSET
PRE-
PROCESSING
RGB
SEPARATION
(INCL.
LINE
MEMORIES)
RGB
PROCESSING
DIGITAL
OUTPUT
FORMATTER
ANALOG
OUTPUT
PREPROCESSING
PAL/NTSC-
ENCODER
V
DACs
Y-
PROCESSING
UV-
PROCESSING
RGB
TO
YUV
2
CLK2
47
RESET
31
to
33
T2,
T1,
T0
MODE
CONTROL
MISCELLANEOUS
FUNCTIONS
SAA8110G
MEASUREMENT
ENGINE
30
20
21
25
26,
27
23
24
18
SCLK
CDAC
OUT
CDAC
RBIAS
SDATA
STROBE
SMP
P0,
P1
VH-REFERENCE
WINDOW
TIMING
AND
CONTROL
34
5
FI
IN
73
77
75
74
VSYNC
IN
HSYNC
IN
SCL/SN
CL
SDA
A0/SN
DA
A1/SN
RES
SNERT/I
2
C
INTERFACE
SNERT/
I2
C
SELECT
Y0
to
Y7
UV0
to
UV7
70
to
63
43
VSYNC
OUT
44
HREF
28
80
49
50
48
52
51
61
to
54
OUT3
to
OUT1
DECOUPL
RBIAS
SIS
79
X
IN
X
OUT
35,
37,
39
LLC
CREF/PXQ
FI
OUT
Fig.1
Block
diagram.
相關(guān)PDF資料
PDF描述
935232410557 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
935232410518 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
935256670557 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
0711 35 A, MODULAR TERMINAL BLOCK
0715 30 A, MODULAR TERMINAL BLOCK
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