參數(shù)資料
型號： 935247890557
廠商： NXP SEMICONDUCTORS
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁數(shù)： 11/35頁
文件大小： 228K
代理商： 935247890557
1996 Aug 07
19
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9077H
Additional I2C-bus settings
Table 6
Overview of additional I2C-bus sub-addresses
SA
DATA BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
20H
PRIO
DPAL
MPAL
SPAL
MVRPN1
MVRPN0
SVRPN1
SVRPN0
21H
MHRPO31
MHRPO30
MHRPO21
MHRPO20
MHRPO11
MHRPO10
MHRPO1
MHRPO0
22H
MHRPN31
MHRPN30
MHRPN21
MHRPN20
MHRPN11
MHRPN10
MHRPN1
MHRPN0
23H
MHPIC7
MHPIC6
MHPIC5
MHPIC4
MHPIC3
MHPIC2
MHPIC1
MHPIC0
24H
MVPIC7
MVPIC6
MVPIC5
MVPIC4
MVPIC3
MVPIC2
MVPIC1
MVPIC0
25H
MHDIS07
MHDIS06
MHDIS05
MHDIS04
MHDIS03
MHDIS02
MHDIS01
MHDIS00
26H
MHDIS17
MHDIS16
MHDIS15
MHDIS14
MHDIS13
MHDIS12
MHDIS11
MHDIS10
27H
MHDIS27
MHDIS26
MHDIS25
MHDIS24
MHDIS23
MHDIS22
MHDIS21
MHDIS20
28H
MHDIS37
MHDIS36
MHDIS35
MHDIS34
MHDIS33
MHDIS32
MHDIS31
MHDIS30
29H
MVDIS7
MVDIS6
MVDIS5
MVDIS4
MVDIS3
MVDIS2
MVDIS1
MVDIS0
2AH
SHRPO31
SHRPO30
SHRPO21
SHRPO20
SHRPO11
SHRPO10
SHRPO01
SHRPO00
2BH
SHRPN31
SHRPN30
SHRPN21
SHRPN20
SHRPN11
SHRPN10
SHRPN01
SHRPN00
2CH
SHPIC7
SHPIC6
SHPIC5
SHPIC4
SHPIC3
SHPIC2
SHPIC1
SHPIC0
2DH
SVPIC7
SVPIC6
SVPIC5
SVPIC4
SVPIC3
SVPIC2
SVPIC1
SVPIC0
2EH
SHDIS07
SHDIS06
SHDIS05
SHDIS04
SHDIS03
SHDIS02
SHDIS01
SHDIS00
2FH
SHDIS17
SHDIS16
SHDIS15
SHDIS14
SHDIS13
SHDIS12
SHDIS11
SHDIS10
30H
SHDIS27
SHDIS26
SHDIS25
SHDIS24
SHDIS23
SHDIS22
SHDIS21
SHDIS20
31H
SHDIS37
SHDIS36
SHDIS35
SHDIS34
SHDIS33
SHDIS32
SHDIS31
SHDIS30
32H
SVDIS7
SVDIS6
SVDIS5
SVDIS4
SVDIS3
SVDIS2
SVDIS1
SVDIS0
Additional I2C-bus register and PIP modes become
available in sub addresses 20H to 32H.
An overview of these I2C-bus registers is given in Table 6.
The meaning and relation of the I2C-bus registers is shown
in Fig.8. The background has a fixed size and can be fine
positioned with BGHFP and BGVFP bits. The shown PIPs
are only for one channel (main or sub), the other channel
has the same control and can be displayed at the same
time. The SDHFP and MDHFP bits determine the most left
shown pixel for this channel in 256 steps of 4 pixels.
The SDVFP and MDVFP bits determine the most upper
shown pixel for this channel in 256 steps of 1 line.
The SHPIC and MHPIC bits determine the horizontal
picture size in 256 steps of 4 pixels, the minimum value is
4 pixels. The SVPIC and MVPIC bits determine the vertical
picture size in 256 steps of 1 line, the minimum value is
1 line. The PIP mode is built-up of a maximum of four
horizontal rows. The minimum is one row, more rows can
be displayed by setting the vertical repetition rate number
VRPN bits.
The distance between the rows can be set by the SVDIS
and MVDIS bits. Every row is built-up of a maximum of four
PIPs. The minimum is one PIP, additional PIPs can be
added with the HRPN values. The SHRPO and MHRPO
bits determine the offset distance between the starting
points of the first PIP. The distances between the starting
points of the PIPs on a row are determined by the SHDIS
and MHDIS bits.
SA 20H CONTROL REGISTER
The PRIO bit sets the priority between main and sub
channel. If PRIO is set to logic 0 priority is given to the sub
channel which means that the sub channel PIPs, if
present, are placed on top of the main PIPs. If PRIO is set
to logic 1 it places the main PIPs on top of the sub PIPs.
The DPAL bit sets the correct default values for PAL on the
display side. The background is enlarged from
238 lines/field to 288 lines/field.
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