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參數(shù)資料
| 型號： | 935233970518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 噪聲抑制 |
| 英文描述： | B Type, DOLBY NOISE REDUCTION IC, PDSO32 |
| 封裝： | 7.50 MM, PLASTIC, SOT-287-1, SOP-32 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 228K |
| 代理商： | 935233970518 |
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1998 Mar 13
8
Philips Semiconductors
Product specication
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I2S-bus Interfaces and system clock
I2S-BUS BASICS
Fig.5 I2S-bus timing and format.
handbook, full pagewidth
Tcy
tLC≥0.35 T
tsr≥0.2 T
thr≥0
tHC≥0.35 T
VIH (70%)
VIL (20%)
VIH (70%)
VIL (20%)
SCK
MBH173
SD
SCK
WS
SD
WS
MSB
RIGHT
MSB
LEFT
For communication with external digital sources and or
additional external processors the I2S-bus digital interface
bus is used. It is a serial 3-line bus, with one line for data,
one line for clock and one line for the word select.
Figure 5 shows an excerpt of the Philips I2S-bus
specification interface report regarding the general timing
and format of I2S-bus. Word Select (WS) logic 0 means left
channel word, logic 1 means right channel word.
The serial data is transmitted in two’s complement with the
MSB first. One clock period after the negative edge of the
word select line the MSB of the left channel is transmitted.
Data is synchronised with the negative edge of the clock
and latched at the positive edge.
I2S-BUS INPUT CIRCUIT
The I2S-bus input circuits can be configured in the
following way using the SEL-IN1/IN2 bit (see Table 4):
1. I2S input 1 is master
(SEL-IN1/IN2 bit = logic 0(default))
2. I2S input 2 is master (SEL-IN1/IN2 bit = logic 1).
The incoming bit-clock frequency defines the accuracy in
terms of number of bits of the incoming data samples.
The input circuit is designed to accept any number of bits
per channel up to a maximum of 18 bits. The accepted
data format is MSB-first.
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