參數(shù)資料
型號(hào)： 935233970512
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 噪聲抑制
英文描述： B Type, DOLBY NOISE REDUCTION IC, PDSO32
封裝： 7.50 MM, PLASTIC, SOT-287-1, SOP-32
文件頁(yè)數(shù)： 5/31頁(yè)
文件大小： 228K
代理商： 935233970512
1998 Mar 13
13
Philips Semiconductors
Product specication
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I2C-BUS FUNCTION BITS
Input selector control register
The write only, two byte, input selector control register is
located on absolute address 0FFFH (4095) and consists
of 16 bits, starting with bit 0 and ending with bit 15.
Deviation from the I2C-bus specication
1. The data hold time (tHD;DAT) for this device (≥0 ns as
stated in the I2C-bus specification) should be as
follows:
a) For the crystal oscillator mode (SHTCB = 0):
≥
b) For the slave oscillator mode (SHTCB = 0):
≥
c) For the slave oscillator mode (SHTCB = 1):
≥
6
f
xtal
---------
6
f
slave
-------------
3
f
slave
-------------
During the write cycle, the I2C-bus clock frequency must
be reduced.
The I2C-bus clock frequency has the following constraints:
fs > 2 × fIIC
fs =I2S-bus sampling frequency
fIIC =I2C-bus clock frequency.
If this constraint cannot be met, a higher I2C-bus frequency
can be obtained in the following way:
By making the I2C-bus master insert a delay (td) after the
acknowledge pulse (see Fig.11). The delay should be
larger than or equal to 1/fs where fs is the I2S-bus
sampling frequency.
By not using the auto-increment feature. This means
that each data word must be preceded by its intended
destination address.
Fig.11 Timing of reduced I2C-bus frequency.
handbook, full pagewidth
MGE756
ACKNOWLEDGE AFTER WORD
td
auto-increment address register
SCL
SDA
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