參數(shù)資料
型號： 935230920112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： 7.50 MM, PLASTIC, SO-28
文件頁數(shù)： 45/68頁
文件大?。?/td> 234K
代理商： 935230920112
2000 Jan 04
5
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
5
PINNING
Note
1. XTAL1 and XTAL2 pins should be connected to VSS1 via 15 pF capacitors.
SYMBOL
PIN
DESCRIPTION
AD7 to AD0
2, 1, 28 to 23
multiplexed address/data bus
ALE/AS
3
ALE input signal (Intel mode), AS input signal (Motorola mode)
CS
4
chip select input, LOW level allows access to the SJA1000
RD/E
5
RD signal (Intel mode) or E enable signal (Motorola mode) from the microcontroller
WR
6
WR signal (Intel mode) or RD/WR signal (Motorola mode) from the microcontroller
CLKOUT
7
clock output signal produced by the SJA1000 for the microcontroller; the clock
signal is derived from the built-in oscillator via the programmable divider; the clock
off bit within the clock divider register allows this pin to disable
VSS1
8
ground for logic circuits
XTAL1
9
input to the oscillator amplier; external oscillator signal is input via this pin; note 1
XTAL2
10
output from the oscillator amplier; the output must be left open-circuit when an
external oscillator signal is used; note 1
MODE
11
mode select input
1 = selects Intel mode
0 = selects Motorola mode
VDD3
12
5 V supply for output driver
TX0
13
output from the CAN output driver 0 to the physical bus line
TX1
14
output from the CAN output driver 1 to the physical bus line
VSS3
15
ground for output driver
INT
16
interrupt output, used to interrupt the microcontroller; INT is active LOW if any bit of
the internal interrupt register is set; INT is an open-drain output and is designed to
be a wired-OR with other INT outputs within the system; a LOW level on this pin will
reactivate the IC from sleep mode
RST
17
reset input, used to reset the CAN interface (active LOW); automatic power-on reset
can be obtained by connecting RST via a capacitor to VSS and a resistor to VDD
(e.g. C = 1
F; R = 50 k)
VDD2
18
5 V supply for input comparator
RX0, RX1
19, 20
input from the physical CAN-bus line to the input comparator of the SJA1000;
a dominant level will wake up the SJA1000 if sleeping; a dominant level is read, if
RX1 is higher than RX0 and vice versa for the recessive level; if the CBP bit (see
Table 49) is set in the clock divider register, the CAN input comparator is bypassed
to achieve lower internal delays if an external transceiver circuitry is connected to
the SJA1000; in this case only RX0 is active; HIGH is interpreted as recessive level
and LOW is interpreted as dominant level
VSS2
21
ground for input comparator
VDD1
22
5 V supply for logic circuits
相關(guān)PDF資料
PDF描述
935246150005 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
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