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參數(shù)資料
| 型號(hào)： | 935229730551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | 935229730551 |
1999 Sep 16
2
Philips Semiconductors
Product specication
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779H
FEATURES
Two 10-bit ADCs with multiplexed outputs
Two 10-bit DACs with multiplexed inputs
Sampling rate for the ADCs and DACs up to 20 MHz
Digital outputs (for the ADC) and inputs (for the DAC)
are TTL/CMOS compatible
Internal reference voltage regulator
Power dissipation 520 mW
Standby mode.
APPLICATIONS
Wireless communication.
GENERAL DESCRIPTION
The TDA8779 contains two 10-bit high speed ADCs and
two 10-bit DACs for wireless communication (for use in
transceiver modules). This device converts two analog
input signals (channels I and Q) and digital inputs
(D0 to D9) at a maximum sampling rate of 20 MHz.
The input bias voltages for the analog input voltages are
provided internally at the middle code. The analog input
and output voltages are AC coupled.
The data sampling is performed on the rising edge of the
clock for ADCs and DACs.
All reference voltages are generated internally.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA1
analog supply voltage for
the ADC part
4.75
5.0
5.5
V
VCCD1
digital supply voltage for the
ADC part
4.75
5.0
5.5
V
VCCA2
analog supply voltage for
the DAC part
4.75
5.0
5.5
V
VCCD2
digital supply voltage for the
DAC part
4.75
5.0
5.5
V
VCCO
output stage supply voltage
2.7
3.0
3.3
V
ICCA
analog supply current
59
74
85
mA
ICCD
digital supply current
15
23
35
mA
ICCO
output stage supply current
ramp input;
fCLK =20MHz
7
mA
fCLK(ADC)max
maximum clock frequency
for the ADC part
20
MHz
INLA
integral non linearity for the
ADC part
full-scale; ramp input;
fCLK =20MHz
±2.25
±4
LSB
DNLA
differential non linearity for
the ADC part
full-scale; ramp input;
fCLK =20MHz
+1.55 to
0.9 +2.8 to 1.1
LSB
fCLK(DAC)max
maximum clock frequency
for the DAC part
20
MHz
INLD
integral non linearity for the
DAC part
full-scale; ramp input;
fCLK =20MHz
±0.4
±1.25
LSB
DNLD
differential non linearity for
the DAC part
full-scale; ramp input;
fCLK =20MHz
±0.35
±1.5
LSB
Ptot
total power dissipation
520
745
mW
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