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參數(shù)資料
| 型號(hào)： | 935219380551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935219380551 |
1995 Nov 03
7
Philips Semiconductors
Preliminary specication
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
Table 4
Pixel byte sequence of 5 :6:5
For RGB 5 :6:5 video inputs, the video data are just
directly bypassed to triple DACs.
The input video data can be selected to either two’s
complement (I2C-bus DRP-bit = 0) or binary offset
(DRP-bit = 1). The video input format is selected by
I2C-bus bits FMTC1 and FMTC0.
The rising edge of HREF input defines the start of active
video data. When HREF is inactive, the video output will be
blanked.
YUV-TO-RGB MATRIX
The matrix converts YUV data, in accordance with
CCIR-601, to RGB data with approximately 1.5 LSB
deviation to the theoretical values for 8-bit resolution.
TRIPLE 8-BIT DACS
Three identical DACs for R, G and B video outputs are
designed with voltage-drive architecture to provide
high-speed operation of up to 50 MHz conversion data
rate. A Cref(h) pin is provided to allow for one external
de-coupling capacitor to be connected between the
internal reference voltage source and ground.
INPUT
PIXEL BYTE SEQUENCE OF RGB
5:6:5
UV7
G0
UV6
R4
UV5
R3
UV4
R2
UV3
R1
UV2
R0
UV1
G5
UV0
G4
YUV7
G3
YUV6
G2
YUV5
G1
YUV4
B4
YUV3
B3
YUV2
B2
YUV1
B1
YUV0
B0
RGB data
0123
Analog mixers and keying control
The analog mixers are controlled to switch between the
outputs from the video DACs and analog RGB inputs by a
keying signal. The analog RGB inputs need to interface
with analog mixers in the way of DC-coupling, also these
RGB inputs are limited to RGB signals without a sync level
pedestal. The keying control can be enabled by setting I2C
bit KEN = 1. Two kinds of keying are possible to generate:
one is external key (from EXTKEY pin when
KMOD2 to KMOD0 are logic 0), and the other is the
internal pixel colour key (when KMOD2 to KMOD0 are not
logic 0) generated by comparing the input pixel data with
the internal I2C-bus register value KD7 to KD0. Controlled
by KMOD2 to KMOD0 bits, there are 4 ways to compare
the pixel data (see Table 5).
Table 5
KMOD2 to KMOD0
Since only one control register KD7 to KD0 provides the
data value for pixel data comparison, when at 2
× 8-bit or
3
× 8-bit pixel input modes, it is presumed that all input
bytes (lower, middle, or higher) of each pixel must be same
as KD7 to KD0 in order to make graphics colour key
active.
The polarity of EXTKEY can be selected with KINV. With
KINV = 0, EXTKEY = HIGH switches analog mixers to
select DAC outputs. Before the internal keying signal
switches the analog multiplexers, it can be further delayed
up to 7 PCLK cycles with the control bits
KDLY2 to KDLY0.
KMOD2
to
KMOD0
PIXEL TYPE
REMARK
100
8-bit pixel
pseudo colour mode
101
2
× 8-bit pixel
high colour mode 1 with
pixels given at both rising
and falling edges of PCLK
110
2
× 8-bit pixel
high colour mode 2 with
pixels given only at rising
edges of PCLK
111
3
× 8-bit pixel
true colour mode
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