參數(shù)資料
型號(hào)： 935214890129
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 314K
代理商： 935214890129
Philips Semiconductors
Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
15
Table 2.
Register Bit Formats (Continued)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
001
RECEIVED
BREAK*
FRAMING
ERROR*
PARITY
ERROR*
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0x01
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OC
OP7
OP6
OP5
OP4
OP3
OP2
OPCR
0x0D
0 = OPR[7]
1 = TxRDYB
0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
00 = OPR[2]
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
SOPR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x0E
See Note
NOTE: 0 = No Change; 1 = Set
ROPR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x0F
See Note
NOTE: 0 = No Change; 1 = Reset
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OPR
OP 7
OP 6
OP 5
OP 4
OP 3
OP 2
OP 1
OP 0
OPR
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACR
0x04
BRG SET
SELECT
COUNTER/TIMER
MODE AND SOURCE
DELTA
IP 3 INT
DELTA
IP 2 INT
DELTA
IP 1 INT
DELTA
IP 0 INT
0x04
0 = set 1
1 = set 2
See Table 6
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IPCR
0x04
DELTA
IP 3
DELTA
IP 2
DELTA
IP 1
DELTA
IP 0
IP 3
IP 2
IP 1
IP 0
0x04
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
0x05
INPUT
PORT
CHANGE
DELTA
BREAK B
RxRDY/
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDY/
FFULLA
TxRDYA
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IMR
0x05
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDY/
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDY/
FFULLA
INT
TxRDYA
INT
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
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